Semiconductor device

1. A semiconductor device, comprising:

a plurality of first through-substrate vias that are electrically connected to one another in a first interconnect layer in the semiconductor device and penetrate through a substrate structure of the semiconductor device, the semiconductor device configured so that the plurality of first through-substrate vias supply power of a first power supply; and

a plurality of second through-substrate vias that are electrically connected to one another in a second interconnect layer in the semiconductor device and penetrate through the substrate structure, the semiconductor device configured so that the plurality second through-substrate vias supply power of a second power supply different from the first power supply; wherein

the first and second through-substrate vias are arrayed adjacent to one another extending in a first direction to form at least one through-substrate via string.

2. The semiconductor device according to claim 1 , wherein

the at least one through-substrate via string is comprised of a plurality of through-substrate via strings including a first through-substrate via string and a second through-substrate via string;

the first through-substrate vias and the second through-substrate vias contained in the plurality of through-substrate via strings being arrayed staggered relative to each other.

3. The semiconductor device according to claim 2 , wherein

the first through-substrate vias contained in the first and second through-substrate via strings are connected together in the first interconnect layer.

4. The semiconductor device according to claim 3 , wherein

the second through-substrate vias contained in the first and second through-substrate via strings are connected together in the second interconnect layer different from the first interconnect layer.

5. The semiconductor device according to claim 3 , wherein,

to connect the first through-substrate vias together or to connect the second through-substrate vias together, an interconnect that extends obliquely relative to the first direction or a key-shaped interconnect is used.

6. The semiconductor device according to claim 3 , wherein,

the first through-substrate vias contained in the first and second through-substrate via strings are connected together using an interconnect extending within a region corresponding to defined regions of the plurality of interconnect layers containing the first and second through-substrate via strings.

7. The semiconductor device according to claim 6 , wherein,

a shape of a first interconnect connecting together the plurality of the first through-substrate vias in a lowermost interconnect layer when seen in a second direction corresponding to an interconnect layer stack direction, with the substrate structure as a reference, is the same as that of a second interconnect connecting together the plurality of the first through-substrate vias in an uppermost interconnect layer in the second direction.

8. The semiconductor device according to claim 7 , wherein,

an interconnect thicker in thickness than an arraying pitch of the first and second through-substrate vias is used in each intermediate interconnect layer between the lowermost and uppermost interconnect layers.

9. The semiconductor device according to claim 7 , wherein,

a plurality of first contacts connecting to a plurality of bump electrodes corresponding to the plurality of the first through-substrate vias and to the plurality of the second through-substrate vias are provided in the uppermost interconnect layer;

a total number of the first contacts being equal to a total number of the plurality of the first through-substrate vias and the plurality of the second through-substrate vias;

a total number of second contacts in the lowermost interconnect layer, connecting together the first and second through-substrate vias with the interconnect layers in the second direction, is lesser than a total number of the first and second through-substrate vias.

10. A semiconductor device, comprising:

a first through via that penetrates a semiconductor substrate to supply a first power supply voltage;

a second through via that penetrates the semiconductor substrate to supply the second power supply voltage different from the first power supply voltage;

a third through via that penetrates the semiconductor substrate and is formed between the first and second through vias to supply the second power supply voltage; and

a fourth through via that penetrates the semiconductor substrate and is formed between the second and third through vias to supply the first power supply voltage, and

wherein the first and fourth vias are electrically connected to one another in a first interconnect layer in the semiconductor device, and the second and third vias are electrically connected to one another in a second interconnect layer in the semiconductor device.

11. The semiconductor device according to claim 10 , wherein the first to fourth vias are aligned in a straight line.

12. The semiconductor device according to claim 11 , wherein each closest two through substrate vias includes a specific distance.

13. The semiconductor device according to claim 10 , wherein a space between each closest two through substrate vias is free from another through substrate via.

14. A semiconductor device, comprising semiconductor substrate including a first interconnect layer and a second interconnect layer:

a plurality of first through-substrate vias that are electrically connected to one another in the first interconnect layer; and

a plurality of second through-substrate vias that are electrically connected to one another in the second interconnect layer, and

the first through-substrate vias being provided adjacently to the second through-substrate vias, on a line extending in a first direction.