IP Library Granted Patent US 9,124,293
Granted Patent B2
US 9,124,293 · App. 13/914,145 · Granted Sep 1, 2015

Continuous time analogue/digital converter

Inventors: Didier Belot (Rives, FR); Jean-Baptiste Begueret (Merignac, FR); Yann Deval (Bordeaux, FR); Dominique Dallet (Villenave d'Ornon, FR); André Mariano (Bordeaux, FR)
Assignee: STMicroelectronics SA
H03M3/458H03M3/484H03M3/50H03M3/402
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,124,293
App. No.
13/914,145
Granted
Sep 1, 2015
Kind
B2
Abstract

Continuous time analog/digital converter, comprising a sigma delta modulator (MSD 1 ) configured to receive an analog input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD 1 ).

Claims (35)

1. A sigma delta modulator comprising:

a first summer configured to add an analogue input signal to a feedback signal to generate a modified analogue signal;

a high-pass filter configured to filter the modified analogue signal to generate a filtered modified analogue signal; and

a quantizer configured to sample the filtered modified analogue signal to generate a digital signal, the high-pass filter comprising an amplifier coupled between an output of the quantizer and an input of the first summer.

2. The sigma delta modulator of claim 1 further comprising a digital to analogue converter configured to convert the digital signal to generate the feedback signal.

3. The sigma delta modulator of claim 1 , wherein the high-pass filter has a chopping frequency, and wherein the quantizer has sampling frequency, the chopping frequency being half of the sampling frequency.

4. The sigma delta modulator of claim 3 , wherein the sampling frequency is 4 GHz and the chopping frequency is 2 GHz.

5. The sigma delta modulator of claim 1 , wherein the high-pass filter further comprises a first resonator.

6. The sigma delta modulator of claim 5 , wherein the high-pass filter further comprises a second resonator.

7. The sigma delta modulator of claim 1 further comprising a delay component coupled between an output of the quantizer and an input of the first summer.

8. A wireless communication device comprising:

a sigma delta modulator configured to receive an analogue input signal, the sigma delta modulator comprising:

a high-pass filter configured to filter the analogue input signal to generate a filtered analogue signal; and

a quantizer configured to sample the filtered analogue signal to generate a digital signal;

a low noise amplifier comprising an input coupled to an antenna and an output coupled to the sigma delta modulator; and

a digital signal processor configured to receive the digital signal from the sigma delta modulator.

9. The wireless communication device of claim 8 , wherein the high-pass filter has a chopping frequency, and wherein the quantizer has sampling frequency, the chopping frequency being less than the sampling frequency.

10. The wireless communication device of claim 9 , wherein the chopping frequency is equal to half of the sampling frequency.

11. The wireless communication device of claim 8 further comprising:

at least one summer configured to add the analogue input signal to a feedback signal; and

a digital to analogue converter configured to convert the digital signal to generate the feedback signal.

12. The wireless communication device of claim 11 further comprising a delay component coupled between an output of the quantizer and an input of the at least one summer.

13. The wireless communication device of claim 8 , wherein the high-pass filter comprises at least one resonator and at least one variable-gain amplifier.

14. The wireless communication device of claim 8 , wherein the quantizer has a sampling frequency, the sampling frequency being equal to twice the frequency of the analogue input signal.

15. A continuous time analogue/digital converter comprising:

a sigma delta modulator configured to receive an analogue input signal, the sigma delta modulator comprising:

a quantizer having a sampling frequency; and

a high-pass filter having a chopping frequency, the chopping frequency being less than the sampling frequency.

16. The continuous time analogue/digital converter of claim 15 , wherein the sigma delta modulator further comprises at least one summer, and wherein the high-pass filter comprises at least one unit including a resonator and a variable-gain amplifier coupled between an output of the quantizer and an input of the at least one summer, the variable-gain amplifier having a gain set at a value wherein a resonance frequency of the resonator is equal to the chopping frequency.

17. The continuous time analogue/digital converter of claim 16 , wherein the high-pass filter comprises at least one other unit.

18. The continuous time analogue/digital converter of claim 16 , wherein the sigma delta modulator further comprises a delay component coupled between the output of the quantizer and the input of the variable-gain amplifier, the delay component being configured to delay a digital output signal of the quantizer by a period equal to half of the sampling period of the quantizer.

19. The continuous time analogue/digital converter of claim 15 , wherein the chopping frequency is equal to half of the sampling frequency.

20. The continuous time analogue/digital converter of claim 15 , wherein the sigma delta modulator further comprises:

at least one summer having a first input coupled to the analogue input signal and an output coupled to the input of the high-pass filter, an output of the high-pass filter coupled to an input of the quantizer; and

a digital to analogue converter having an input coupled to an output of the quantizer and an output of the digital to analogue converter being coupled to a second input of the at least one summer.

Assignments (5)
CHANGE OF NAME Recorded Dec 8, 2023
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 065835/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2015
From: CENTRE NATIONAL DE RECHERCHE SCIENTIFIQUE (CNRS) 3 RUE MICHEL ANGE PARIS, FRANCE 75016
To: STMICROELECTRONICS SA
Reel/Frame 035757/0024 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2015
From: CENTRE NATIONAL DE RECHERCHE SCIENTIFIQUE (CNRS)
To: STMICROELECTRONICS SA
Reel/Frame 035757/0281 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2015
From: BELOT, DIDIER; BEGUERET, JEAN-BAPTISTE; DEVAL, YANN; DALLET, DOMINIQUE; MARIANO, ANDRE
To: STMICROELECTRONICS SA; CENTRE NATIONAL DE RECHERCHE SCIENTIFIQUE (CNRS)
Reel/Frame 034813/0943 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2014
From: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
To: STMICROELECTRONICS SA
Reel/Frame 033035/0424 →
Priority Claims (1)
FR 10 51011 · Feb 15, 2010 · national
Continuity (2)
Continuation 13024729 · Feb 10, 2011
Related Publication 20130271304A1 · Oct 17, 2013