Thin film transistor panel and method for manufacturing the same

1. A thin film transistor array panel comprising:

an insulation substrate;

a thin film transistor disposed on the insulation substrate, wherein the thin film transistor includes a first electrode;

a first contact hole pattern having an opening of a first width, wherein the first contact hole pattern exposes a portion of the first electrode through the opening; and

a first contact hole exposing the portion of the first electrode,

a first passivation layer disposed on the thin film transistor;

wherein an inner sidewall of the first contact hole pattern constitutes a first portion of the first contact hole,

wherein the first passivation layer includes a sidewall spaced apart from an outer sidewall of the first contact hole pattern to form a space between the first contact hole pattern and the first passivation layer, and

wherein the space between the sidewall of the first passivation layer and the outer sidewall of the first contact hole pattern exposes the portion of the first electrode.

2. The thin film transistor array panel of claim 1 further comprising:

a second passivation layer disposed on the first passivation layer;

a first field generating electrode disposed on the second passivation layer;

a third passivation layer disposed on the first field generating electrode; and

a second field generating electrode disposed on the third passivation layer and connected to the first electrode of the thin film transistor though the first contact hole.

3. The thin film transistor array panel of claim 2 , wherein the first passivation layer includes an inorganic insulating material, and the first contact hole pattern includes a substantially same material as the first passivation layer.

4. The thin film transistor array panel of claim 3 , wherein the second passivation layer includes an organic insulating material.

5. The thin film transistor array panel of claim 2 , wherein a sidewall of the second passivation layer constitutes a second portion of the first contact hole and a sidewall of the third passivation layer constitutes a third portion of the first contact hole.

6. The thin film transistor array panel of claim 1 , wherein a width of the first contact hole pattern is less than about 8 μm.

7. The thin film transistor array panel of claim 2 , further comprising:

a reference voltage line connected to the first field generating electrode; and

a gate insulating layer disposed on the reference voltage line, wherein the first field generating electrode is connected to the reference voltage line through a second contact hole exposing a portion of the reference voltage line.

8. The thin film transistor array panel of claim 7 , further comprising a second contact hole pattern exposing a portion of the reference voltage line and separated from the first passivation layer.

9. The thin film transistor array panel of claim 8 , further comprising a second contact hole to expose the portion of the reference voltage line, wherein a sidewall of the gate insulating layer constitutes a first portion of the second contact hole, an inner sidewall of the second contact hole constitutes a second portion of the second contact hole, and a sidewall of the second passivation layer constitutes a third portion of the second contact hole.

10. The thin film transistor array panel of claim 8 , wherein a width of the second contact hole pattern is less than about 8 μm.

11. The thin film transistor array panel of claim 1 , wherein the second field generating electrode has a plurality of branch electrodes.

12. The thin film transistor array panel of claim 1 , wherein the first contact hole pattern include a circular shape.

13. A method of manufacturing a thin film transistor array panel, comprising:

forming a thin film transistor on an insulation substrate;

forming a first passivation layer on the thin film transistor;

forming a first contact hole pattern having an opening of a first width by patterning the first passivation layer, wherein the first passivation Layer is separated into the first contact hole pattern and a patterned first passivation layer;

forming a second passivation layer having a preliminary contact hole having a second width, wherein the second width is greater than the first width and overlaps the first contact hole pattern, and

reflowing the second passivation layer to form a first contact hole,

wherein an inner sidewall of the first contact hole pattern constitutes a first portion of a sidewall of the first contact hole,

wherein a sidewall of the second passivation layer constitutes a second portion of the sidewall of the first contact hole, the second portion is extended from the first portion of the first contact hole, and

wherein the first contact hole pattern is spaced apart from the patterned first passivation layer to form a space through which a portion of the thin film transistor is exposed.

14. The method of claim 13 , wherein a width of the opening in the first contact hole pattern is less than about 8 μm.

15. The method of claim 13 , wherein the opening of the first contact hole pattern has a circular shape.

16. The method of claim 13 , further comprising:

forming a first field generating electrode on the second passivation layer;

forming a third passivation layer including a third portion of the first contact hole extended from the second portion of the first contact hole on the first field generating electrode; and

forming a second field generating electrode connected to the thin film transistor through the first contact hole on the third passivation layer.

17. The method of claim 13 , wherein the first passivation layer includes an inorganic insulating material, and the first contact hole pattern includes a substantially same material as the first passivation layer.

18. The method of claim 13 , wherein the second passivation layer includes an organic insulating material.