Digital receiver
View Patent ↗A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.
1. A receiver comprising:
a sampler operable to separate a radio frequency signal into a plurality of phased analog signals, wherein the plurality of phased analog signals comprises N parallel phased analog signals, N being an integer multiple of 4, and wherein the sampler comprises a polyphase filter, the polyphase filter comprising N sub-filters, each sub-filter being operable to filter a respective analog signal of the plurality of phased analog signals;
a sigma delta analog to digital converter system operable to convert the plurality of phased analog signals into a plurality of phased digital signals; and
a digital downconverter operable to combine and downconvert the plurality of phased digital signals into downconverted digital signal.
2. The receiver as recited in claim 1 wherein the polyphase filter comprises a digital finite impulse response filter.
3. The receiver as recited in claim 1 , wherein:
the digital signal comprises I and Q signals; and
filter coefficients of the sub-filters are selected such that the sub-filters operate as a demodulator for generating the I and Q signals.
4. The receiver as recited in claim 1 , further comprising a local oscillator coupled to the sampler, the local oscillator being operable to generate a local clocking signal for use in separating the radio frequency signal into the plurality of phased analog signals.
5. The receiver as recited in claim 1 , further comprising:
a low noise amplifier operable to amplify a radio frequency input signal; and
an analog bandpass filter operable to filter the amplified radio frequency input signal to produce the radio frequency signal.
6. The receiver as recited in claim 1 , further comprising a rate change element operable to change an input sampling rate associated with the I and Q signals to a different output sampling rate associated with the I and Q signals.
7. The receiver as recited in claim 6 , wherein the input sampling rate is a sub-multiple of the output sampling rate.
8. A computer-implemented method comprising:
sampling and separating a radio frequency signal into a plurality of phased analog signals, wherein the plurality of phased analog signals comprises N parallel phased analog signals, N being an integer multiple of 4, and wherein the sampling is based, at least in part, on a polyphase filter, the polyphase filter comprising N sub-filters, each sub-filter being operable to filter a respective analog signal of the plurality of phased analog signals;
converting the plurality of phased analog signals into a plurality of phased digital signals using a sigma delta analog to digital converter system; and
combining and downconverting the plurality of phased digital signals into downconverted digital signal.
9. The computer-implemented method as recited in claim 8 wherein the polyphase filter comprises a digital finite impulse response filter.
10. The computer-implemented method as recited in claim 8 , wherein:
the digital signal comprises I and Q signals; and
filter coefficients of the sub-filters are selected such that the sub-filters operate as a demodulator for generating the I and Q signals.
11. The computer-implemented method as recited in claim 8 , further comprising generating a local clocking signal for use in separating the radio frequency signal into the plurality of phased analog signals.
12. The computer-implemented method as recited in claim 8 , further comprising:
amplifying a radio frequency input signal; and
filtering the amplified radio frequency input signal to produce the radio frequency signal.
13. The computer-implemented as recited in claim 8 , further comprising changing an input sampling rate associated with the I and Q signals to a different output sampling rate associated with the I and Q signals.
14. The computer-implemented method as recited in claim 13 , wherein the input sampling rate is a sub-multiple of the output sampling rate.
15. Program instructions stored on hardware which, responsive to execution, cause the hardware to:
separate a radio frequency signal into a plurality of phased analog signals, wherein the plurality of phased analog signals comprises N parallel phased analog signals, N being an integer multiple of 4, and wherein the sample comprises a polyphase filter, the polyphase filter comprising N sub-filters, each sub-filter being operable to filter a respective analog signal of the plurality of phased analog signals;
convert the plurality of phased analog signals into a plurality of phased digital signals using a sigma delta analog to digital converter system; and
combine and downconvert the plurality of phased digital signals into downconverted digital signal.
16. The program instructions as recited in claim 15 , wherein the polyphase filter comprises a digital finite impulse response filter.
17. The program instructions as recited in claim 15 , wherein:
the digital signal comprises I and Q signals; and
filter coefficients of the sub-filters are selected such that the sub-filters operate as a demodulator for generating the I and Q signals.
18. The program instructions as recited in claim 15 , the receiver further configured to generate a local clocking signal for use in separating the radio frequency signal into the plurality of phased analog signals.
19. The program instructions as recited in claim 16 , the receiver further configured to:
amplify a radio frequency input signal; and
filter the amplified radio frequency input signal to produce the radio frequency signal.
20. The program instructions as recited in claim 16 , the receiver further configured to change an input sampling rate associated with the I and Q signals to a different output sampling rate associated with the I and Q signals.