IP Library Granted Patent US 8,775,687
Granted Patent B1
US 8,775,687 · App. 13/917,299 · Granted Jul 8, 2014

Method to ensure data coherency in a scalable aggregate neighbor-device interface

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Quick Facts
Patent No.
US 8,775,687
App. No.
13/917,299
Granted
Jul 8, 2014
Kind
B1
Abstract

A method for processing a read sub-command in a secondary storage controller is disclosed. The method includes receiving the read sub-command from a primary storage controller; retrieving data in response to the read sub-command; utilizing a write request to write the retrieved data directly to a memory accessible by a host device; issuing an additional request to the same memory after the write request; receiving an indication of completion of the additional request; and reporting a sub-completion status to the primary storage controller.

Claims (49)

1. A method for processing read sub-command, the method comprising:

receiving at least one read sub-command from a primary storage controller, the at least one read sub-command being generated by the primary storage controller in response to a read command from a host device;

retrieving data in response to each of the at least one read sub-command;

utilizing at least one write request to write the retrieved data directly to a memory accessible by the host device;

issuing an additional request to the same memory after the at least one write request;

receiving an indication of completion of the additional request; and

reporting a sub-completion status to the primary storage controller.

2. The method of claim 1 , wherein each of the at least one write request is a Peripheral Component Interconnect Express (PCIe) write request to the memory accessible by the host device.

3. The method of claim 2 , wherein the additional request issued to the same memory after the at least one write request is a non-posted PCIe request.

4. The method of claim 3 , wherein the non-posted PCIe request is a PCIe read request.

5. The method of claim 3 , wherein the non-posted PCIe request is a zero-length read request.

6. The method of claim 2 , wherein the memory accessible by the host device is accessible through a PCIe root complex, and wherein the additional request is issued to the PCIe root complex.

7. A storage apparatus, comprising:

a plurality of storage devices; and

a plurality of storage controllers configured for controlling the plurality of storage devices;

wherein one of the plurality of storage controllers is configured as a primary storage controller and the rest of the plurality of storage controllers are configured as secondary storage controllers;

wherein the primary storage controller is configured for accepting a host device initiated command and generating a sub-command for at least one of the secondary storage controllers; and

wherein the at least one of the secondary storage controller is configured for:

receiving the sub-command from the primary storage controller;

determining whether the sub-command is a read sub-command or a write sub-command;

retrieving data in response to the read sub-command;

utilizing at least one write request to write the retrieved data directly to a memory accessible by the host device;

issuing an additional request to the same memory after the at least one write request;

receiving an indication of completion of the additional request; and

reporting a sub-completion status to the primary storage controller.

8. The storage apparatus of claim 7 , wherein each of the plurality of storage controllers implements a Peripheral Component Interconnect Express (PCIe) communication protocol.

9. The storage apparatus of claim 8 , wherein each of the at least one write request is a PCIe write request to the memory accessible by the host device.

10. The storage apparatus of claim 8 , wherein the additional request issued to the same memory after the at least one write request is a non-posted PCIe request.

11. The storage apparatus of claim 9 , wherein the non-posted PCIe request is a PCIe read request or a zero-length read request.

12. The storage apparatus of claim 8 , wherein the memory accessible by the host device is accessible through a PCIe root complex, and wherein the additional request is issued to the PCIe root complex.

13. The storage apparatus of claim 7 , wherein each of the plurality of storage devices includes a solid state drive.

14. A method for processing a host device initiated command, the method comprising:

accepting a host device initiated command at a primary storage controller;

generating a sub-command for at least one secondary storage controller;

processing the sub-command utilizing said at least one secondary storage controller, further comprising:

determining whether the sub-command is a read sub-command or a write sub-command;

retrieving data in response to the read sub-command;

utilizing at least one write request to write the retrieved data directly to a memory accessible by the host device;

issuing an additional request to the same memory after the at least one write request;

receiving an indication of completion of the additional request; and

reporting a sub-completion status to the primary storage controller;

collecting the sub-completion status from each of said at least one secondary storage controller; and

reporting an aggregated completion status to the host device when the sub-completion status from each of said at least one secondary storage controller is received.

15. The method of claim 14 , wherein each of the primary storage controller and the at least one secondary storage controller implements a Peripheral Component Interconnect Express (PCIe) communication protocol.

16. The method of claim 15 , wherein each of the at least one write request is a PCIe write request to the memory accessible by the host device.

17. The method of claim 15 , wherein the additional request issued to the same memory after the at least one write request is a non-posted PCIe request.

18. The method of claim 17 , wherein the non-posted PCIe request is a PCIe read request or a zero-length read request.

19. The method of claim 15 , wherein the memory accessible by the host device is accessible through a PCIe root complex, and wherein the additional request is issued to the PCIe root complex.

20. The method of claim 14 , wherein each of the plurality of storage devices includes a logical storage device or a physical storage device.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Mar 19, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 035226/0230 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2013
From: LIU, YANG; PATWA, NITAL; XU, CHANGYOU; CANEPA, TIMOTHY; CHEN, CHIEN
To: LSI CORPORATION
Reel/Frame 030644/0518 →