Method of fabricating electronic component

1. A method of fabricating an electronic component, the method comprising:

mounting a device chip on an upper surface of an insulative substrate;

forming a sealing portion that seals the device chip;

cutting the insulative substrate and the sealing portion; and

forming a plated layer covering the sealing portion by barrel plating,

wherein the sealing portion is formed of an insulating material, and

the forming of the plated layer includes forming a first plated layer on a surface of the sealing portion by electroless barrel plating and then forming a second plated layer on a surface of the first plated layer by electrolytic barrel plating.

2. The method according to claim 1 , further comprising:

forming a resist layer covering a terminal located on a bottom surface of the insulative substrate before the forming of the plated layer; and

removing the resist layer after the forming of the plated layer.

3. The method according to claim 1 , wherein

the forming of the sealing portion includes forming the sealing portion along a side surface and an upper surface of the device chip.

4. A method of fabricating an electronic component, the method comprising:

mounting a device chip on an upper surface of an insulative substrate:

forming a sealing portion that seals the device chip;

cutting the insulative substrate and the sealing portion; and

forming a plated layer covering the sealing portion by barrel plating, wherein

a terminal is located on a bottom surface of the insulative substrate that is an opposite surface to the upper surface of the insulative substrate, and

the cutting includes cutting the insulative substrate and the sealing portion from a side of the bottom surface of the insulative substrate.

5. The method according to claim 4 , wherein

the sealing portion includes a metal, and

the forming of the plated layer includes forming the plated layer by electrolytic barrel plating.

6. The method according to claim 5 , wherein

the plated layer includes a material same as that of the terminal located on the bottom surface of the insulative substrate.

7. The method according to claim 5 , wherein

the forming of the plated layer includes forming a first plated layer covering the sealing portion and a second plated layer contacting with the terminal located on the bottom surface of the insulative substrate, and

the method further comprises removing the second plated layer so that the terminal is exposed after the forming of the plated layer.

8. The method according to claim 4 , wherein

the forming of the plated layer includes forming a first plated layer covering the sealing portion and a second plated layer covering the terminal located on the bottom surface of the insulative substrate, and

the first plated layer and the second plated layer are formed of copper.

9. The method according to claim 4 , further comprising:

forming a first plated layer formed of copper on the terminal located on the bottom surface of the insulative substrate;

forming a resist layer covering the first plated layer before the forming of the plated layer; and

removing the resist layer after the forming of the plated layer.

10. The method according to claim 4 , wherein

the insulative substrate includes internal wiring,

the forming of the plated layer includes forming the plated layer by electrolytic barrel plating under a state where a grounding wiring out of the internal wiring is not exposed from the insulative substrate.

11. The method according to claim 10 , wherein

the forming of the plated layer is performed under a state where a grounding wiring and a signal wiring out of the internal wiring are not exposed from the insulative substrate.

12. The method according to claim 4 , further comprising:

forming a resist layer covering the terminal located on the bottom surface of the insulative substrate before the forming of the plated layer; and

removing the resist layer after the forming of the plated layer.

13. The method according to claim 4 , wherein

the forming of the sealing portion includes forming the sealing portion along a side surface and an upper surface of the device chip.