Magnetoresistive random-access memory

1. A memory device, comprising:

a magnetic storage element; and

an access transistor, coupled to the magnetic storage element, having a first gate and a second gate,

wherein the first gate and the second gate are configured to be isolated electrically from each other, and

wherein the first gate is configured to activate the access transistor and the second gate is configured to adjust a threshold voltage value of the access transistor;

a word line coupled to the access transistor; and

first and second fin field effect transistor (FinFET) based sources,

wherein the first FinFET based source is configured to be at a greater potential than the second FinFET based source to orient a magnetization direction of the magnetic storage element in a first direction corresponding to a logical one or at a lesser potential than the second FinFET based source to orient the magnetization direction of the magnetic storage element in a second direction corresponding to a logical zero, and

wherein the access transistor is configured to be activated, in response to controlling the word line, to provide a first current from the first FinFET based source to the second FinFET based source to orient the magnetization direction of the magnetic storage element in the first direction or to provide a second current from the second FinFET based source to the first FinFET based source to orient the magnetization direction of the magnetic storage element in the second direction.

2. The memory device of claim 1 , wherein the word line comprises a first word line and a second word line configured to control the access transistor, and

wherein the first word line and the second word line are respectively coupled to a terminal of the first gate and a terminal of the second gate.

3. The memory device of claim 2 , wherein the first word line and the second word line are configured to apply a voltage value to the first gate terminal and the second gate terminal, respectively, based on a mode of operation of the memory device.

4. The memory device of claim 1 , further comprising:

a sense amplifier;

a select line coupled to the access transistor; and

a bit line coupled to the magnetic storage element and the sense amplifier.

5. The memory device of claim 1 , wherein the access transistor is a dual gate FinFET.

6. The memory device of claim 1 , wherein the magnetic storage element comprises a first ferromagnetic layer and a second ferromagnetic layer, the first ferromagnetic layer and the second ferromagnetic layer being separated by an insulating layer and having magnetization directions parallel or perpendicular to the second ferromagnetic layer and the first ferromagnetic layer, respectively.

7. The memory device of claim 6 , wherein the first ferromagnetic layer comprises a magnetization that is fixed in a predetermined direction, and

wherein the second ferromagnetic layer comprises a magnetization that changes directions based on current applied to the magnetic storage element.

8. The memory device of claim 1 , wherein the magnetic storage element comprises a single barrier magnetic tunnel junction (MTJ) device.

9. The memory device of claim 1 , wherein the magnetic storage element comprises a double barrier magnetic tunnel junction (MTJ) device.

10. The memory device of claim 1 , wherein the first FinFET based source is a first current source, and wherein the second FinFET based source is a second current source.

11. The memory device of claim 1 , further comprising a second magnetic storage element connected electrically in series with the magnetic storage element and located between the access transistor and a bit line.

12. The memory device of claim 1 , wherein the second gate is configured to adjust the threshold voltage value based on a mode of operation of the memory device.

13. A memory device, comprising:

an access transistor having a source region, a drain region, a first gate region, and a second gate region on a top surface of a planar substrate;

a first magnetic storage element and a second magnetic storage element,

wherein the first magnetic storage element is stacked on the second magnetic storage element between a bit line and the source region or the drain region;

a word line coupled to the access transistor; and

first and second fin field effect transistor (FinFET) based sources,

wherein the first FinFET based source is configured to be at a greater potential than the second FinFET based source to orient magnetization directions of the first and second magnetic storage elements in a first direction corresponding to a logical one or at a lesser potential than the second FinFET based source to orient the magnetization directions of the first and second magnetic storage elements in a second direction corresponding to a logical zero, and

wherein the access transistor is configured to be activated, in response to controlling the word line, to provide a first current from the first FinFET based source to the second FinFET based source to orient the magnetization directions of the first and second magnetic storage elements in the first direction or to provide a second current from the second FinFET based source to the first FinFET based source to orient the magnetization directions of the first and second magnetic storage elements in the second direction.

14. The memory device of claim 13 , further comprising a plurality of conducting layers stacked and coupled to the source region and the drain region, running parallel to the top surface of the planar substrate.

15. The memory device of claim 14 , wherein a conducting layer of a first stack of the plurality of conducting layers comprises a bit line, and

wherein a conducting layer of a second stack of the plurality of conducting layers comprises a select line.

16. The memory device of claim 14 , wherein at least a conducting layer of the plurality of conducting layers is configured to electrically couple a first ferromagnetic layer of the first magnetic storage element to a second ferromagnetic layer of the second magnetic storage element.

17. The memory device of claim 13 , wherein the first magnetic storage element and the second magnetic storage element have at least two ferromagnetic layers separated by an insulating layer, the at least two ferromagnetic layers comprising magnetization directions parallel or perpendicular to the surface of the planar substrate.

18. The memory device of claim 13 , wherein the first magnetic storage element and the second magnetic storage element comprise:

magnetic tunnel junction (MTJ) devices.

19. The memory device of claim 13 , wherein the first gate region and the second gate region are configured to be electrically isolated from each other.

20. The memory device of claim 13 , wherein the first gate region and the second gate region are capacitively coupled to a first side and a second side of a fin region of the access transistor, respectively.

21. A memory device, comprising:

a fin field effect transistor (FinFET) having a source region and a drain region;

a stack of conducting layers on the source region or the drain region;

a stack of magnetic tunnel junction (MTJ) devices on the stack of conducting layers;

a word line coupled to the FinFET; and

first and second FinFET based sources,

wherein the first FinFET based source is configured to be at a greater potential than the second FinFET based source to orient magnetization directions of the stack of MTJ devices in a first direction corresponding to a logical one or at a lesser potential than the second FinFET based source to orient the magnetization directions of the stack of MTJ devices in a second direction corresponding to a logical zero, and

wherein the FinFET is configured to be activated, in response to controlling the word line, to provide a first current from the first FinFET based source to the second FinFET based source to orient the magnetization directions of the stack of MTJ devices in the first direction or to provide a second current from the second FinFET based source to the first FinFET based source to orient the magnetization directions of the stack of MTJ devices in the second direction.

22. The memory device of claim 21 , wherein the stack of MTJ devices comprises:

a first MTJ device positioned between a bit line and the stack of conducting layers; and

a second MTJ device positioned between the bit line and the first MTJ device.