Opaque bridge for peripheral component interconnect express bus systems

1. A system comprising:

a PCIe (Peripheral Component Interconnect Express) subsystem comprising PCIe devices; and

a host coupled to the PCIe subsystem, and configured to:

during setup of the PCIe subsystem, load custom driver software (SW) corresponding to a non-PCI bus protocol, and configure the PCIe devices according to the custom driver SW instead of configuring the PCIe devices according to a PCI bus driver; and

subsequent to the setup of the PCIe subsystem, load existing PCIe device drivers to operate the PCIe devices.

2. The system of claim 1 , wherein during setup of the PCIe subsystem, the host is configured to:

execute a BIOS (basic input/output system), wherein the BIOS is informed that the PCIe devices to be coupled to the host are not PCIe devices, and is further informed how much memory is required by the PCIe devices to be coupled; and

in executing the BIOS, allocate the required memory to the PCIe devices.

3. The system of claim 1 , wherein the host is configured to execute an OS (operating system), and load the custom driver SW while executing the OS.

4. The system of claim 1 , further comprising a bus extender that couples the PCIe subsystem to the host;

wherein the bus extender appears to the host as a bridge to a bus of unknown type.

5. The system of claim 4 , wherein the host is further configured to:

prior to loading the custom driver SW, preallocate specified one or more memory ranges to the bus extender.

6. The system of claim 5 , wherein the bus extender comprises a configuration space register configured to store a list of resource requests intended for the host;

wherein the host is further configured to preallocate the specified one or more memory ranges to the bus extender according to the list of resource requests stored in the configuration space register.

7. The system of claim 5 , wherein when configuring the PCIe devices according to the custom driver SW, the host uses the preallocated specified one or more memory ranges to configure memory requirements for the PCIe devices.

8. A system comprising:

a processing element; and

a memory configured to store:

first driver software corresponding to a non-PCI (non Peripheral Component Interconnect) bus protocol and executable by the processing element during setup of a PCIe (PCI Express) subsystem that comprises PCIe devices to be coupled to a host system; and

PCIe device driver software executable by the processing element subsequent to the setup of the PCIe subsystem;

wherein the processing element is configured to:

execute the first driver software to configure the PCIe devices; and

execute the PCIe driver software to operate the PCIe devices.

9. The system of claim 8 , wherein the processing element and the memory are comprised in the host system.

10. The system of claim 8 , wherein the memory is further configured to store:

basic input/output system (BIOS) software executable by the processing element during the setup of the PCIe subsystem;

wherein the processing element is configured to execute the BIOS software prior to executing the first driver software to preallocate specified resources associated with the PCIe subsystem.

11. The system of claim 10 , wherein the processing element is further configured to execute the first driver software to use the preallocated specified resources to configure memory requirements for the PCIe devices.

12. The system of claim 10 , further comprising:

a bus extender configured to couple the PCIe subsystem to the host system;

wherein the bus extender appears to the processing element as a bridge to a bus of unknown type.

13. The system of claim 10 , wherein the bus extender comprises a configuration space register configured to store a list of resource requests intended for the processing element;

wherein the processing element is further configured to execute the BIOS software prior to executing the first driver software to preallocate the specified resources to the bus extender according to the list of resource requests stored in the configuration space register.

14. A method for configuring and operating PCIe (Peripheral Component Interconnect Express) devices comprised in a PCIe subsystem coupled to a host system, the method comprising:

preallocating specified one or more memory ranges to a bus extender appearing to the host system as a bridge to a bus of unknown type;

configuring memory requirements of the PCIe devices, said configuring comprising:

using the preallocated specified one or more memory ranges; and

configuring the memory requirements without recognizing that the memory requirements are intended for PCIe devices.

15. The method of claim 14 , further comprising:

exposing the PCIe devices to the host system as PCIe devices, subsequent to said configuring the memory requirements of the PCIe devices.

16. The method of claim 14 , wherein said preallocating is performed according to resource requirements stored in a configuration space register.

17. The method of claim 16 , further comprising:

writing, by the bus extender, the resource requirements into the configuration space register.

18. The method of claim 14 , wherein said preallocating is performed by executing a basic input/output system (BIOS).

19. The method of claim 14 , wherein said configuring the memory requirements of the PCIe devices is performed by loading driver software by an operating system;

wherein the driver software corresponds to a non-PCI bus protocol.

20. The method of claim 14 , further comprising operating the PCIe devices by loading and executing PCIe device drivers, subsequent to said preallocating and said configuring the memory requirements of the PCIe devices.