Nanoprojector panel formed of an array of liquid crystal cells

1. A nanoprojector panel formed of an array of cells, each cell comprising a liquid crystal layer between upper and lower transparent electrodes, a MOS control transistor being arranged above the upper electrode, each transistor being covered with at least three metallization levels, wherein:

the transistor of each cell extends in a corner of the cell so that the transistors of an assembly of four adjacent cells are arranged in a central region of said assembly;

the upper metallization level extends above the transistors of each said assembly of four adjacent cells; and

the panel comprises, for each said assembly of four adjacent cells, a first conductive ring surrounding the transistors, the first ring extending from the lower metallization level to the upper electrode of each cell with an interposed insulating material.

2. The panel of claim 1 , further comprising, for each said assembly of four adjacent cells, a second conductive ring and a third conductive ring surrounding the MOS control transistors and extending above the first conductive ring, the second ring extending from the intermediate metallization level to the lower metallization level and the third ring extending from the upper metallization level to the intermediate metallization level.

3. The panel of claim 1 , further comprising, for each cell, a conductive via extending from a metallization of the lower metallization level, connected to a main electrode of the MOS control transistor, to the upper transparent electrode.

4. The panel of claim 1 , wherein the width of the first conductive ring ranges between 0.2 and 0.3 μm.

5. The panel of claim 1 , wherein the insulating material is silicon oxide and has a thickness ranging between 1 and 5 nm.

6. A method for manufacturing a panel formed of an array of cells intended to be used in a nanoprojector, comprising the steps of:

starting from a wafer comprising a semiconductor substrate covered with a first insulating layer itself covered with a semiconductor layer;

forming MOS control transistors in active areas of the semiconductor layer, the rest of the semiconductor layer being oxidized, the transistor of each cell being formed in a corner of the cell so that the transistors of an assembly of four adjacent cells are arranged in a central region of said assembly;

depositing a second insulating layer on the structure and forming first openings surrounding the transistors of each said assembly of four adjacent cells, from the upper surface of the second insulating layer all the way to the substrate;

filling the first openings with a conductive material to form first conductive rings;

forming at least three metallization levels above each transistor, metallizations of the lower metallization level being formed above the first conductive ring, the upper metallization level being formed so as to continuously cover the transistors of each said assembly of four adjacent cells;

bonding the surface of the structure supporting the metallization levels to a first transparent plate and removing the substrate to expose the first conductive rings;

forming an insulating material above each first conductive ring;

for each cell, covering the first insulating layer and the insulating material with a first transparent electrode;

on a second transparent plate, forming a second transparent electrode; and

assembling the first and second plates, so that the first and second transparent electrodes are in front of each other, with an interposed liquid crystal layer.

7. The method of claim 6 , further comprising, at the step of forming of the metallization levels above each MOS control transistor, the steps of:

forming a second conductive ring above the first conductive ring, from the intermediate metallization level to the lower metallization level; and

forming a third conductive ring above the second conductive ring, from the upper metallization level to the intermediate metallization level.

8. The method of claim 6 , wherein:

at the step of forming of the first openings surrounding the MOS control transistors of each said assembly of four adjacent cells, second openings are formed from the upper surface of the second insulating layer to reach the substrate;

at the step of filing of the first openings, the second openings are filled with the conductive material to form vias; and

at the step of forming of the metallization levels, metallizations of the lower metallization level are formed above the vias.