Virtual Chassis Topology Management
Topology management within a virtual chassis is achieved by communicating virtual chassis topology information between switches within the virtual chassis within protocol extensions of customized protocol data units (PDUs) associated with a VC-ISIS protocol. The virtual chassis topology information can be used, for example, to detect the topology of the virtual chassis and generate a shortest path tree within each switch of the virtual chassis for use in routing between switches within the virtual chassis.
1 . A switch within a virtual chassis including at least two switches, the switch comprising:
a plurality of virtual fabric link (VFL) ports coupled to a VFL, wherein the VFL interconnects each of the at least two switches within the virtual chassis to enable the at least two switches to operate as a single logical switch;
a processor for:
receiving a customized protocol data unit (PDU) from an additional switch within the virtual chassis via one of the VFL ports,
extracting virtual chassis topology information from protocol extensions within the PDU, and
using the virtual chassis topology information to detect a topology of the virtual chassis and generate a shortest path tree for use in routing within the virtual chassis.
2 . The switch of claim 1 , wherein the customized PDU is one of a customized Hello PDU and a customized Link State PDU and the protocol extensions are type length value fields within the customized PDU.
3 . The switch of claim 2 , wherein the customized Hello PDU includes a sub-second Hello interval within one of the type length value fields that indicates a sub-second time interval between successive customized Hello PDUs transmitted from the additional switch.
4 . The switch of claim 1 , wherein the VFL ports are coupled to respective VFL links, each coupling the switch to one of the other at least two switches.
5 . The switch of claim 1 , wherein the processor further uses the virtual chassis topology information within the customized PDU and additional virtual chassis topology information within additional customized PDUs received from other ones of the switches within the virtual chassis to detect each of the at least two switches within the virtual chassis.
6 . The switch of claim 1 , wherein the processor further uses the virtual chassis topology information to elect a master switch for the virtual chassis from the at least two switches.
7 . The switch of claim 6 , wherein the processor elects the master switch using one or more of a switch priority of the additional switch, an uptime of the additional switch, an identifier of the additional switch and a Media Access Control (MAC) address of the additional switch, each included within the virtual chassis topology information.
8 . The switch of claim 1 , wherein the virtual chassis includes at least six switches coupled to each other in a mesh topology.
9 . The switch of claim 1 , further comprising:
a memory maintaining forwarding tables; and
wherein the processor programs the shortest path tree into the forwarding tables.
10 . The switch of claim 1 , wherein the processor further uses the virtual chassis topology information to detect a failure of one or more of the at least two switches within the virtual chassis and to generate a new shortest path tree upon detection of the failure.
11 . The switch of claim 1 , wherein the virtual chassis topology information includes:
an identifier of the additional switch;
a MAC address of the additional switch;
an indication of whether the additional switch is a master switch or a slave switch;
a type of the additional switch;
a slot identifier identifying a network interface slot of the additional switch to which the switch is coupled;
a Virtual Local Area Network (VLAN) identifier of a VLAN managed by the additional switch; and
a sub-second time interval between successive PDUs transmitted from the additional switch.
12 . The switch of claim 1 , wherein the virtual chassis topology information includes one or more of:
an identifier of at least one chassis management module within the additional switch;
an uptime of the additional switch;
license information for software configured on the additional switch;
a switch priority of the additional switch;
an identifier of the virtual chassis;
an identifier of a master switch within the virtual chassis; and
an identifier of a candidate master switch within the virtual chassis.
13 . A non-transitory memory device having tangibly embodied thereon and accessible therefrom a set of instructions interpretable by at least one processor, the set of instructions configured for causing the processor to carry out operations for:
receiving customized protocol data units (PDUs) from switches within a virtual chassis at a receiving one of the switches via one of a plurality of VFL ports, the plurality of VFL ports being coupled to a VFL, wherein the VFL interconnects each of the switches within the virtual chassis to enable the switches to operate as a single logical switch;
extracting virtual chassis topology information from protocol extensions within the customized PDUs; and
using the virtual chassis topology information to detect a topology of the virtual chassis and generate a shortest path tree for use in routing between the switches within the virtual chassis.
14 . The memory of claim 13 , wherein:
the customized PDUs include at least one of customized Hello PDUs and customized Link State PDUs and the protocol extensions are type length value fields within the customized PDUs; and
the customized Hello PDUs each include a sub-second Hello interval within one of the type length value fields that indicates a sub-second time interval between successive customized Hello PDUs transmitted by each of the switches within the virtual chassis.
15 . The memory of claim 13 , wherein the set of instructions further causes the processor to carry out operations for:
using the virtual chassis topology information within the customized PDUs to detect each of the switches within the virtual chassis.
16 . The memory of claim 13 , wherein the set of instructions further causes the processor to carry out operations for:
using the virtual chassis topology information to elect a master switch for the virtual chassis from the at least two switches.
17 . The memory of claim 13 , wherein the set of instructions further causes the processor to carry out operations for:
using the virtual chassis topology information to detect a failure of one or more of the at least two switches within the virtual chassis and to generate a new shortest path tree upon detection of the failure.
18 . The memory of claim 13 , wherein the virtual chassis topology information within a customized PDU received from a transmitting switch within the virtual chassis includes:
an identifier of the transmitting switch;
a MAC address of the transmitting switch;
an indication of whether the transmitting switch is a master switch or a slave switch;
a type of the transmitting switch;
a slot identifier identifying a network interface slot of the transmitting switch to which the switch is coupled;
a Virtual Local Area Network (VLAN) identifier of a VLAN managed by the transmitting switch; and
a sub-second time interval between successive PDUs transmitted from the transmitting switch.
19 . The memory of claim 13 , wherein the virtual chassis topology information within a customized PDU received from a transmitting switch within the virtual chassis includes:
an identifier of at least one chassis management module within the transmitting switch;
an uptime of the transmitting switch;
license information for software configured on the transmitting switch;
a switch priority of the transmitting switch;
an identifier of the virtual chassis;
an identifier of a master switch within the virtual chassis; and
an identifier of a candidate master switch within the virtual chassis.
20 . A method for topology management within a virtual chassis, comprising:
receiving customized protocol data units (PDUs) from switches within the virtual chassis at a receiving one of the switches via one of a plurality of VFL ports, the plurality of VFL ports being coupled to a VFL, wherein the VFL interconnects each of the switches within the virtual chassis to enable the switches to operate as a single logical switch;
extracting virtual chassis topology information from protocol extensions within the customized PDUs; and
using the virtual chassis topology information to detect a topology of the virtual chassis and generate a shortest path tree for use in routing between the switches within the virtual chassis.