Four terminal transistor fabrication
Producing a transistor includes providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate including a reentrant profile is formed from an electrically conductive material layer stack provided on the first electrically insulating material layer in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. The gate including the reentrant profile and at least a portion of the first electrically insulating material layer are conformally coated with a second electrically insulating material layer. The second electrically insulating material layer is conformally coated the with a semiconductor material layer. A source and drain electrodes are formed simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer.
1. A method of producing a transistor comprising:
providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer;
providing an electrically conductive material layer stack on the first electrically insulating material layer;
forming a gate including a reentrant profile from the electrically conductive material layer stack in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate;
conformally coating the gate including the reentrant profile and at least a portion of the first electrically insulating material layer with a second electrically insulating material layer;
conformally coating the second electrically insulating material layer with a semiconductor material layer; and
forming source and drain electrodes simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer.
2. The method of claim 1 , further comprising forming a plurality of transistors on the substrate using the method of claim 1 , wherein the first electrically conductive material layer is patterned to be associated with at least one discrete transistor of the plurality of transistors.
3. The method of claim 1 , wherein forming the gate including the reentrant profile from the electrically conductive material layer stack includes using a plasma etchant to remove a portion of the electrically conductive material layer stack.
4. The method of claim 1 , wherein forming the gate including the reentrant profile from the electrically conductive material layer stack includes using a liquid etchant to remove a portion of the electrically conductive material layer stack.
5. The method of claim 1 , the substrate including a first layer and a second layer, the method further comprising:
removing the second layer of the substrate.
6. The method of claim 1 , wherein the substrate is flexible.