MOS transistor on SOI protected against overvoltages
A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.
1. A MOS transistor device comprising:
a semiconductor substrate and insulating layer thereon and an SOI-type semiconductor layer on the insulating layer;
a MOS transistor comprising a gate electrode above the SOI-type semiconductor layer and source and drain regions in said SOI-type semiconductor layer on opposite sides of said gate electrode; and
a lateral field-effect-controlled thyristor comprising a cathode contact region and anode contact region within the substrate at least partly under the MOS transistor, a field effect turn-on region of the thyristor extending under at least a portion of the gate electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode contact region and the cathode contact region of the lateral field-effect controlled thyristor being respectively connected to the drain region and to the source region of the MOS transistor, wherein the lateral field-effect controlled thyristor turns on in case of a positive overvoltage between the drain and the source regions of the MOS transistor, and a first well of a first conductivity type and a second well of the second conductivity type extending next to each other in the substrate below the cathode contact region and anode contact region of the lateral field-effect-controlled thyristor and a junction between the first and second wells turns on when a positive overvoltage occurs between the source region and drain region of the MOS transistor.
2. The MOS transistor device of claim 1 , wherein the field-effect turn-on region of the thyristor corresponds to its cathode contact region and extends under at least a portion of the drain region of the MOS transistor.
3. The MOS transistor device of claim 1 , wherein the field-effect turn-on region of the thyristor corresponds to its anode contact region and extends under at least a portion of the source region of the MOS transistor.
4. The MOS transistor device of claim 1 , comprising:
first and second regions of the second conductivity type respectively extending at the surface of the first and second wells, the first and second regions being separated from each other by a portion of the first well corresponding to the field-effect turn-on region of the thyristor.
5. The MOS transistor device of claim 4 , wherein:
the first and second wells are respectively P-type doped and N-type doped;
the cathode contact region of the lateral field-effect controlled thyristor corresponds to a third N-type region more heavily doped than the first region, extending at the surface of the first well next to the first region and in contact therewith; and
the anode contact region of the thyristor corresponds to a fourth heavily-doped P-type region extending at the surface of the second well next to the second region and in contact therewith.
6. The MOS transistor device of claim 4 , wherein:
the first and second wells are respectively P-type doped and N-type doped;
the cathode contact region of the lateral field-effect controlled thyristor corresponds to a third N-type region more heavily doped than the first region, extending above the first region and in contact therewith; and
the anode contact region of the lateral field-effect controlled thyristor corresponds to a fourth heavily-doped P-type region extending above the second region and in contact therewith.
7. The MOS transistor device of claim 4 , wherein:
the substrate is P-type doped;
the first and second wells are respectively N-type doped and P-type doped;
the anode contact region of the lateral field-effect controlled thyristor corresponds to a third P-type region more heavily doped than the first region, extending at the surface of the first well next to the first region and in contact therewith;
the cathode contact region of the lateral field-effect controlled thyristor corresponds to a fourth heavily-doped N-type region extending at the surface of the second well next to the second region and in contact therewith and
an N-type buried layer extends at least under the second well.
8. The MOS transistor device of claim 5 , wherein a first terminal connected to the first well is connected to the cathode contact region of the lateral field-effect controlled thyristor, and wherein a second terminal connected to the second well is connected to the anode contact region of the thyristor.
9. The MOS transistor device of claim 7 , wherein a first terminal connected to the first well is connected to the anode contact region of the lateral field-effect controlled thyristor, and wherein a second terminal connected to the second well is connected to the cathode contact region of the lateral field-effect controlled thyristor.
10. The MOS transistor device of claim 1 , wherein the thickness of the SOI-type semiconductor layer ranges between 3 and 100 nm and wherein the thickness of the insulating layer ranges between 5 and 30 nm.