IP Library Granted Patent US 9,201,106
Granted Patent B1
US 9,201,106 · App. 13/923,037 · Granted Dec 1, 2015

Self shielding capacitance sensing panel

Inventors: Min Chin Chai (Lynnwood, WA); Fred Keiser (San Jose, CA); Igor Polishchuk (Fremont, CA)
Assignee: PARADE TECHNOLOGIES, LTD.
G01R27/2605G06F3/044
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Quick Facts
Patent No.
US 9,201,106
App. No.
13/923,037
Granted
Dec 1, 2015
Kind
B1
Abstract

A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source.

Claims (29)

1. An apparatus, comprising:

a first plurality of sensor elements;

a second plurality of sensor elements, wherein each of the first plurality of sensor elements is capacitively coupled with each of the second plurality of sensor elements, and wherein each of the second plurality of sensor elements comprises a plurality of sub-elements; and

wherein the first plurality of sensor elements are configured to shield each of the second plurality of sensor elements from a noise source.

2. The apparatus of claim 1 , wherein substantially all of an area of the second plurality of sensor elements overlaps an area of the first plurality of sensor elements.

3. The apparatus of claim 1 , wherein all of the plurality of sub-elements in each separate sensor element of the second plurality of sensor elements are electrically connected to one another.

4. The apparatus of claim 1 , wherein the plurality of sub-elements comprises three parallel sub-elements.

5. The apparatus of claim 1 , wherein the plurality of sub-elements comprises two parallel sub-elements.

6. The apparatus of claim 5 , wherein each of the two parallel sub-elements comprises one or more extension traces extending from a respective sub-element.

7. The apparatus of claim 6 , wherein the one or more extension traces extending from each sub-element are interleaved with each one another.

8. An apparatus, comprising:

a first plurality of sensor elements separated by a first width between each of the first plurality of sensor elements; and

a second plurality of sensor elements separated by a second width between each of the second plurality of sensor elements, wherein the first width is less than the second width, wherein each of the second plurality of sensor elements comprises a plurality of sub-elements, and wherein the first plurality of sensor elements is situated between the second plurality of sensor elements and a noise source.

9. The apparatus of claim 8 , wherein substantially all of the area of the second plurality of sensor elements overlaps an area of the first plurality of sensor elements.

10. The apparatus of claim 8 , wherein each of the first plurality of sensor elements is capacitively coupled to each of the second plurality of sensor elements, wherein each of the first plurality of sensor elements is configured to transmit a signal, and wherein each of the second plurality of sensor elements is configured to receive the transmitted signal.

11. The apparatus of claim 8 , wherein the noise source comprises a liquid crystal display (LCD) panel, and wherein the plurality of sub-elements comprise metal traces located between pixels of the LCD panel.

12. The apparatus of claim 8 , wherein the plurality of sub-elements comprises three linear parallel sub-elements.

13. The apparatus of claim 8 , wherein the plurality of sub-elements comprises two linear parallel sub-elements.

14. The apparatus of claim 13 , wherein each of the two linear parallel sub-elements comprises one or more extension traces extending from a respective linear sub-element.

15. The apparatus of claim 14 , wherein the one or more extension traces extending from each linear sub-element are interleaved with each one another.

16. An apparatus, comprising:

a first plurality of sensor elements;

a noise source located adjacent to a first side of the plurality of sensor elements;

a second plurality of sensor elements located adjacent to a second side of the first plurality of sensor elements, the first side opposite the second side, wherein noise from the noise source is blocked from the second plurality of sensor elements by the first plurality of sensor elements, and wherein each of the second plurality of sensor elements comprises a plurality of sub-elements; and

a capacitance sensing system coupled with the first plurality of sensor elements and the second plurality of sensor elements, wherein the capacitive sensing system is configured to measure mutual capacitances between each of the first plurality of sensor elements and each of the second plurality of sensor elements.

17. The apparatus of claim 16 , wherein the capacitance sensing system is configured to measure the mutual capacitances by applying a transmit signal to each of the first plurality of sensor elements and measuring a receive signal at each of the second plurality of sensor elements.

18. The apparatus of claim 16 , wherein the plurality of sub-elements to increase a fringe electric field between the first plurality of sensor elements and the second plurality of sensor elements.

19. The apparatus of claim 16 , wherein the plurality of sub-elements comprises parallel sub-elements.

20. The apparatus of claim 19 , wherein each of the plurality of parallel sub-elements comprises one or more extension traces extending from a respective sub-element, and wherein the one or more extension traces extending from each sub-element are interleaved with each one another.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION
To: PARADE TECHNOLOGIES, LTD.
Reel/Frame 036508/0284 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS AND TRADEMARKS Recorded Aug 4, 2015
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT FOR THE SECURED PARTIES
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036264/0114 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
PATENT SECURITY AGREEMENT Recorded Nov 14, 2013
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 031636/0105 →
Continuity (3)
Continuation 13172749 · Jun 29, 2011
Provisional Application 61478346 · Apr 22, 2011
Provisional Application 61360305 · Jun 30, 2010