IP Library Granted Patent US 8,711,952
Granted Patent B2
US 8,711,952 · App. 13/925,239 · Granted Apr 29, 2014

Analog to digital converter with increased sub-range resolution

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Quick Facts
Patent No.
US 8,711,952
App. No.
13/925,239
Granted
Apr 29, 2014
Kind
B2
Abstract

An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

Claims (38)

1. A communication device comprising:

a processing module;

memory coupled to the processing module;

a communication interface coupled to the processing module, the communication interface comprising:

an analog front end configured to produce an analog communication signal;

a digital front end configured to receive a digital communication signal; and

an Analog to Digital Converter (ADC) configured to sample the analog communication signal across a full-range, the ADC comprising:

a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range;

a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range; and

signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

2. The communication device of claim 1 , wherein the central sub-range corresponds to an expected range of the analog communication signal.

3. The communication device of claim 1 , wherein the central sub-range corresponds to approximately a middle quarter of the full-range.

4. The communication device of claim 1 , wherein the central sub-range ADC and the full-range ADC have a common bit size output.

5. The communication device of claim 1 , wherein the analog front end further comprises:

a Programmable Gain Amplifier (PGA) configure to be responsive to a gain input and to gain adjust the analog communication signal; and

gain control circuitry configured to produce the gain input so that the analog communication signal is within an expected range.

6. The communication device of claim 1 , wherein the communication interface is configured to service Powerline Communications.

7. The communication device of claim 1 , wherein the ADC further comprises range adjusting circuitry configured to select the central sub-range.

8. A method for operating a communication device comprising:

producing an analog communication signal by an analog front end;

sampling a full-range of the analog communication signal by a full-range ADC having a first quantization accuracy to produce a full-range ADC output;

sampling a central sub-range of the analog communication signal by a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy to produce a central sub-range ADC output; and

processing outputs of the full-range ADC output and the central sub-range ADC output to create a digital communication signal.

9. The method of claim 8 , wherein the central sub-range corresponds to an expected range of the analog communication signal.

10. The method of claim 8 , wherein the central sub-range corresponds to approximately a middle quarter of the full-range.

11. The method of claim 8 , wherein the central sub-range ADC output and the outer sub-range ADC output have a common bit size output.

12. The method of claim 8 , further comprising gain adjusting the analog communication signal in an attempt to cause the analog communication signal to be in the central sub-range.

13. The method of claim 8 , wherein the analog communication signal is a Powerline Communication signal.

14. The method of claim 8 , further comprising adjusting the central sub-range.

15. An Analog to Digital Converter (ADC) that samples an analog signal comprising:

a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across a full-range;

a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range; and

signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create a digital communication signal.

16. The ADC of claim 15 , wherein the central sub-range corresponds to an expected range of the analog signal.

17. The ADC of claim 15 , wherein the central sub-range corresponds to approximately a middle quarter of the full-range.

18. The ADC of claim 15 , wherein the central sub-range ADC and the full-range ADC have a common bit size output.

19. The ADC of claim 15 , wherein the ADC is configured to service Powerline Communications.

20. The ADC of claim 15 , further comprising range adjusting circuitry configured to select the central sub-range.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2013
From: FINDLATER, KEITH; DANESH, SEYED AA; HURWITZ, JONATHAN EPHRAIM DAVID
To: BROADCOM CORPORATION
Reel/Frame 030673/0190 →