Semiconductor device
View Patent ↗A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
1. A clock synchronous semiconductor device, comprising:
a data terminal which receives data;
an input buffer having a differential amplifier coupled to said data terminal; and
a plurality of memory cells, each of which is necessary to refresh,
wherein the differential amplifier has:
an input terminal for receiving an input enable signal,
an output terminal for outputting received data,
a power supply transistor for supplying a first supply voltage,
a pre-charge transistor connected between the output terminal and a pre-charge voltage, and
an inverter connected between the output terminal and the pre-charge transistor,
wherein, in a time period from a write command issuing to a next command issuing, said input enable signal is changed from an active state to an inactive state.
2. A clock synchronous semiconductor device according to claim 1 ,
wherein in the active state the power supply transistor is turned on and the pre-charge transistor is turned off; and
wherein in the inactive state the power supply transistor is turned off and the pre-charge transistor is turned on.
3. A clock synchronous semiconductor device according to claim 1 ,
wherein in the time period from the write command issuing to the next command issuing, the input enable signal is changed from the active state to the inactive state after write data are written to the memory cells.