Method and system for error correction in flash memory
View Patent ↗A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal.
1. A controller for a multi-level, solid-state, non-volatile memory having memory cells, the memory cells configured to store data using a first number of digital levels, the controller comprising:
a first encoder configured to generate second data, in response to first data, for storage in the multi-level, solid-state, non-volatile memory, wherein
voltages of the memory cells that are programmed to a first level of the digital levels are described by a first probability density function having a first width,
voltages of the memory cells that are programmed to a second level of the digital levels are described by a second probability density function having a second width,
the first width is greater than the second width, and
the first encoder is configured to reduce a first frequency of the first level in the second data compared to a second frequency of the second level in the second data; and
an analog-to-digital converter configured to, in response to one of the memory cells of the multi-level, solid-state, non-volatile memory, output a respective digital signal,
wherein the respective digital signal is selected from a second number of digital levels that is greater than the first number of digital levels.
2. The controller of claim 1 , further comprising a first decoder configured to decode the respective digital signal to create decoded digital signals.
3. The controller of claim 2 , further comprising a second encoder configured to generate the first data in response to input data.
4. The controller of claim 3 , further comprising a second decoder configured to further decode the decoded digital signals.
5. The controller of claim 3 , wherein the first encoder includes a low-density parity-check encoder and wherein the second encoder includes a Reed-Solomon encoder.
6. The controller of claim 3 , wherein the first encoder is configured to perform a first ECC technique and the second encoder is configured to perform a second ECC technique, wherein the first ECC technique is different than the second ECC technique.
7. The controller of claim 1 , wherein the first encoder performs first encoding using soft information.
8. The controller of claim 1 , wherein the first encoder includes at least one of a trellis-coded modulation encoder, a binary encoder, a convolutional encoder, a low-density parity-check encoder, and an iterative encoder.
9. The controller of claim 1 , wherein the multi-level, solid-state, non-volatile memory includes flash memory.
10. An integrated circuit comprising the controller of claim 1 .
11. A method for operating a multi-level, solid-state, non-volatile memory having memory cells, the memory cells configured to store data using a first number of digital levels, the method comprising:
generating second data, in response to first data, for storage in the multi-level, solid-state, non-volatile memory using a first encoder, wherein
voltages of the memory cells that are programmed to a first level of the digital levels are described by a first probability density function having a first width,
voltages of the memory cells that are programmed to a second level of the digital levels are described by a second probability density function having a second width, and
the first width is greater than the second width;
reducing a first frequency of the first level in the second data compared to a second frequency of the second level in the second data;
outputting a respective digital signal in response to one of the memory cells of the multi-level, solid-state, non-volatile memory; and
selecting the respective digital signal from a second number of digital levels that is greater than the first number of digital levels.
12. The method of claim 11 , further comprising decoding the respective digital signal to create decoded digital signals using a first decoder.
13. The method of claim 12 , further comprising generating the first data in response to input data using a second encoder.
14. The method of claim 13 , further comprising decoding the decoded digital signals using a second decoder.
15. The method of claim 13 , wherein the first encoder includes a low-density parity-check encoder and wherein the second encoder includes a Reed-Solomon encoder.
16. The method of claim 13 , wherein the first encoder is configured to perform a first ECC technique and the second encoder is configured to perform a second ECC technique, wherein the first ECC technique is different than the second ECC technique.
17. The method of claim 11 , wherein the first encoder performs first encoding using soft information.
18. The method of claim 11 , wherein the first encoder includes at least one of a trellis-coded modulation encoder, a binary encoder, a convolutional encoder, a low-density parity-check encoder, and an iterative encoder.
19. The method of claim 11 , wherein the multi-level, solid-state, non-volatile memory includes flash memory.