INTERCONNECT STRUCTURE FOR MOLDED IC PACKAGES
Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an interposer. A plurality of conductive elements provide physical and electrical contact between a surface of the substrate and a surface of the interposer. A standoff element disposed between the surfaces of the substrate and interposer provides a minimum spacing between the surfaces of the substrate and interposer. In some implementations, a standoff element is disposed between an IC die disposed on the surface of the substrate and the surface of the interposer. In another example, a method includes coupling conductive elements to a surface of an interposer, attaching a standoff element, coupling the conductive elements to a surface of a substrate, and forming an embedded layer between the interposer and substrate. The standoff element defines a minimum gap between the interposer and the substrate.
1 . An integrated circuit (IC) package, comprising:
a substrate including a first surface and a second surface opposite the first surface;
an interposer including a first surface and a second surface opposite the first surface;
a plurality of homogeneous solder balls disposed between the first surface of the substrate and the second surface of the interposer, the plurality of homogeneous solder balls providing physical and electrical contact between the substrate and the interposer; and
a standoff element disposed between the first surface of the substrate and the second surface of the interposer, the standoff element providing a predefined minimum spacing between the first surface of the substrate and the second surface of the interposer.
2 . The IC package of claim 1 , further comprising an IC die disposed between the first surface of the substrate and the second surface of the interposer.
3 . The IC package of claim 2 , wherein the standoff element is located between the IC die and an inner row of the homogenous solder balls.
4 . The IC package of claim 2 , wherein the standoff element is located between an outer row of the homogenous solder balls and an outer edge of the IC package.
5 . The IC package of claim 1 , further comprising a plurality of standoff elements disposed between the first surface of the substrate and the second surface of the interposer, the plurality of standoff elements providing a predefined minimum spacing between the first surface of the substrate and the second surface of the interposer.
6 . The IC package of claim 1 , wherein the standoff element is a standoff post comprising dummy silicon.
7 . The IC package of claim 1 , wherein the standoff element is a passive element.
8 . The IC package of claim 1 , wherein the standoff element is attached to the second surface of the interposer.
9 . The IC package of claim 1 , further comprising an embedded layer disposed between and in contact with the first surface of the substrate and the second surface of the interposer, the embedded layer encapsulating the plurality of homogeneous solder balls and at least a portion of the standoff element.
10 . An integrated circuit (IC) package, comprising:
a substrate including a first surface and a second surface opposite the first surface;
an interposer including a first surface and a second surface opposite the first surface;
a plurality of homogeneous solder balls disposed between the first surface of the substrate and the second surface of the interposer, the plurality of homogeneous solder balls providing physical and electrical contact between the substrate and the interposer;
an IC die disposed on the first surface of the substrate, and
a standoff element disposed between the IC die and the second surface of the interposer, the standoff element providing a predefined minimum spacing between the IC die and the second surface of the interposer.
11 . The IC package of claim 10 , wherein the standoff element is a standoff post comprising dummy silicon.
12 . The IC package of claim 11 , wherein the standoff post is attached to the second surface of the interposer.
13 . The IC package of claim 11 , wherein the standoff post is attached to a surface of the IC die.
14 . The IC package of claim 10 , wherein the standoff element is a solder mask attached to the second surface of the interposer.
15 . The IC package of claim 10 , wherein the standoff element is a passive element attached to the second surface of the interposer.
16 . The IC package of claim 1 , further comprising an embedded layer disposed between and in contact with the first surface of the substrate and the second surface of the interposer, the embedded layer encapsulating the plurality of homogeneous solder balls, the IC die, and at least a portion of the standoff element.
17 . A method of manufacturing an integrated circuit (IC) package, comprising:
coupling a plurality of conductive elements to a surface of an interposer;
attaching a standoff element to the surface of the interposer or the substrate;
coupling the plurality of conductive elements to a surface of a substrate, the standoff element defining a minimum gap between the surface of the interposer and the surface of the substrate; and
injecting encapsulation material between the surface of the interposer and the surface of the substrate to form an embedded layer in contact with the surface of the interposer and the surface of the substrate, the embedded layer encapsulating the plurality of conductive elements and at least a portion of the standoff element.
18 . The method of claim 17 , wherein the standoff element is positioned between the surface of the interposer and an IC die coupled to the surface of the substrate.
19 . The method of claim 18 , further comprising coupling the IC die to the surface of the substrate.
20 . The method of claim 17 , further comprising singulation of the IC package wherein the standoff element is removed from the IC package during singulation.