Asymmetrical bus keeper

1. An asymmetrical bus keeper circuit comprising:

a first inverter stage having an input node and an output node;

an asymmetrical inverter stage having an input node and an output node; the input node of the asymmetrical inverter stage being connected to the output node of the first inverter stage; and

a feedback stage with an input node and an output node, the input node of the feedback stage being connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage being connected to the input node of the first inverter stage,

wherein the asymmetrical inverter stage provides an asymmetrical drive towards one logic level and the feedback stage comprises a resistor.

2. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a single p-channel transistor wherein a gate of the p-channel transistor is connected to the input node of the asymmetrical inverter stage, a source of the p-channel transistor is connected to a positive voltage supply level, and a drain of the p-channel transistor is connected to the output node of the asymmetrical inverter stage.

3. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a p-channel transistor having a first drive and an n-channel transistor having a second drive, the p-channel and n-channel transistors being oriented in an inverter configuration, wherein the first drive is at least one order of magnitude larger than the second drive.

4. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical inverter stage comprises a single n-channel transistor wherein a gate of the n-channel transistor is connected to the input node of the asymmetrical inverter stage, a source of the n-channel transistor is connected to ground, and a drain of the n-channel transistor is connected to the output node of the asymmetrical inverter stage.

5. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical inverter stage comprises a p-channel transistor having a first drive and an n-channel transistor having a second drive, the p-channel and n-channel transistors being oriented in an inverter configuration, wherein the second drive is at least one order of magnitude larger than the first drive.

6. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical bus keeper circuit further comprises a pull-up resistor connected between the input node of the first inverter stage and a positive voltage supply level.

7. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical bus keeper circuit further comprises a pull-down resistor connected between the input node of the first inverter stage and ground.

8. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical bus keeper circuit further comprises a resistor connected between the output node of the asymmetrical inverter stage and the positive voltage supply level.

9. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level and the asymmetrical bus keeper circuit further comprises a resistor connected between the output node of the asymmetrical inverter stage and ground.

10. The asymmetrical bus keeper circuit of claim 1 , wherein the symmetrical and asymmetrical inverter stages comprise bipolar junction transistors and the asymmetrical inverter stage comprises a totem pole output structure with only an upper portion having a bipolar junction transistor to provide the asymmetrical drive to a high logic level.

11. The asymmetrical bus keeper circuit of claim 1 , wherein the symmetrical and asymmetrical inverter stages comprise bipolar junction transistors and the asymmetrical inverter stage comprises a totem pole output structure with only a lower portion having a bipolar junction transistor to provide the asymmetrical drive to a low logic level.

12. The asymmetrical bus keeper circuit of claim 1 , wherein the symmetrical and asymmetrical inverter stages comprise bipolar junction transistors and the asymmetrical inverter stage comprises a totem pole output structure with an upper portion having a bipolar junction transistor with a first drive and a lower portion having a bipolar junction transistor with a second drive, wherein the first drive is at least one order of magnitude larger than the second drive to provide the asymmetrical drive to a high logic level.

13. The asymmetrical bus keeper circuit of claim 1 , wherein the symmetrical and asymmetrical inverter stages comprise bipolar junction transistors and the asymmetrical inverter stage comprises a totem pole output structure with an upper portion having a bipolar junction transistor with a first drive and a lower portion having a bipolar junction transistor with a second drive, wherein the second drive is at least one order of magnitude larger than the first drive to provide the asymmetrical drive to a low logic level.

14. The asymmetrical bus keeper circuit of claim 1 , wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level and the asymmetrical inverter stage comprises a first transistor having a first drive and an second transistor having a second drive, wherein the first drive is at least one order of magnitude larger than the second drive.

15. An asymmetrical bus keeper circuit comprising:

a first inverter stage having an input node and an output node;

an asymmetrical inverter stage having an input node, a single p-channel transistor and an output node, a gate of the p-channel transistor being connected to the input node of the asymmetrical inverter stage, a source of the p-channel transistor being connected to a positive voltage supply level, a drain of the p-channel transistor being connected to the output node of the asymmetrical inverter stage and the input node of the asymmetrical inverter stage being connected to the output node of the first inverter stage; and

a feedback stage with an input node and an output node, the input node of the feedback stage being connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage being connected to the input node of the first inverter stage,

wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a high logic level.

16. The asymmetrical bus keeper circuit of claim 15 , wherein the asymmetrical bus keeper circuit further comprises a pull-up resistor connected between the input node of the first inverter stage and a positive voltage supply level.

17. The asymmetrical bus keeper circuit of claim 15 , wherein the asymmetrical bus keeper circuit further comprises a resistor connected between the output node of the asymmetrical inverter stage and the positive voltage supply level.

18. An asymmetrical bus keeper circuit comprising:

a first inverter stage having an input node and an output node;

an asymmetrical inverter stage having an input node, a single n-channel transistor and an output node, a gate of the n-channel transistor being connected to the input node of the asymmetrical inverter stage, a source of the n-channel transistor being connected to ground, a drain of the n-channel transistor being connected to the output node of the asymmetrical inverter stage, and the input node of the asymmetrical inverter stage being connected to the output node of the first inverter stage; and

a feedback stage with an input node and an output node, the input node of the feedback stage being connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage being connected to the input node of the first inverter stage,

wherein the asymmetrical inverter stage is configured to provide the asymmetrical drive to a low logic level.

19. The asymmetrical bus keeper circuit of claim 18 , wherein the asymmetrical bus keeper circuit further comprises a pull-down resistor connected between the input node of the first inverter stage and ground.

20. The asymmetrical bus keeper circuit of claim 18 , wherein the asymmetrical bus keeper circuit further comprises a resistor connected between the output node of the asymmetrical inverter stage and ground.