System and method for efficient buffer management for banked shared memory designs
A system and method for efficient buffer management for banked shared memory designs are provided. In one embodiment, a controller within the switch is configured to manage the buffering of the shared memory banks by allocating full address sets to write sources. Each full address set that is allocated to a write source includes a number of memory addresses, wherein each memory address is associated with a different shared memory bank. A size of the full address set can be based on a determined number of buffer access contenders.
1. A switch, comprising:
a first number of write sources;
a second number of read sources;
a plurality of shared memory banks that facilitate access by the first number of write sources and the second number of read sources; and
a controller that is configured to allocate full address sets to one of the first number of write sources, wherein each full address set includes a third number of memory addresses, each memory address in the third number of memory addresses being associated with a different shared memory bank, the third number being at least as large as the first number, the controller being further configured to monitor a fourth number of full address sets that are available to the first of the plurality of write sources, and to generate a flow control message based on the monitoring,
wherein the one of the first number of write sources selects one of the memory addresses from a full address set when writing a packet to a shared memory bank.
2. The switch of claim 1 , wherein the third number is equal to the first number.
3. The switch of claim 1 , wherein the third number is equal to the first number plus the second number.
4. The switch of claim 1 , wherein the controller implements a write first policy.
5. The switch of claim 1 , wherein the controller implements a read first policy.
6. A method performed by a switch, comprising:
allocating full address sets to one of a first number of write sources that writes packets to a plurality of shared memory banks, a second number of read sources reading the packets from the plurality of shared memory banks, wherein each full address set includes a third number of memory addresses, each memory address in the third number of memory addresses being associated with a different shared memory bank, the third number being at least as large as the first number;
selecting, by the one of the first number of write sources, one of the memory addresses from a full address set;
writing, by the one of the first number of write sources, a packet to a shared memory bank at the selected memory address, wherein the writing of the packet to the selected memory addresses removes a status of the address set containing the selected memory address as a full address set;
monitoring a fourth number of full address sets that are available to the first of the plurality of write sources; and
generating a flow control message based on the monitoring.
7. The method of claim 6 , wherein the third number is equal to the first number.
8. The method of claim 6 , wherein the third number is equal to the first number plus the second number.
9. The method of claim 6 , further comprising changing, after the writing, a designation of the address set containing the selected memory address from a full address set to a partial address set.
10. The method of claim 6 , wherein the monitoring comprises comparing the fourth number to a threshold value.
11. A method performed by a switch, comprising:
selecting, by one of a first number of write sources that write packets to a plurality of shared memory banks, one of a plurality of full address sets that are available to the one of the first number of write sources, a second number of read sources reading packets from the plurality of shared memory banks, wherein each full address set includes a third number of memory addresses, each memory address in the third number of memory addresses being associated with a different shared memory bank, the third number being at least as large as the first number;
writing, by the one of the first number of write sources, a packet to a shared memory bank at one of the memory addresses in the selected one of the plurality of full address sets;
reducing, based on the writing, a number of full address sets that are available to the one of the first number of write sources;
monitoring the number of full address sets that are available to the first of the plurality of write sources; and
generating a flow control message based on the monitoring.
12. The method of claim 11 , wherein the third number is equal to the first number.
13. The method of claim 11 , wherein the third number is equal to the first number plus the second number.
14. The method of claim 11 , further comprising changing, after the writing, a designation of the address set containing the selected memory address from a full address set to a partial address set.
15. The method of claim 11 , wherein the monitoring comprises comparing the monitored number of full address sets to a threshold value.