Voltage protection scheme for semiconductor devices
View Patent ↗Various examples are provided for voltage protection of semiconductor devices. In one example, among others, a circuit includes a MOS device, a protective device connected between the MOS device and an output voltage connection, and gate protection circuitry configured to provide a bias voltage to a gate of the protective device. The bias voltage includes a DC bias component and an AC bias component that synchronously varies with a voltage of the output voltage connection. Another example includes a plurality of protective devices connected between the MOS device and the output voltage connection. The gate protection circuitry may be configured to provide a plurality of bias voltages to the plurality of protective devices. In another example, a method includes attenuating an output voltage, combining the attenuated output voltage with a constant offset voltage to generate a gate bias voltage, and providing the gate bias voltage to a protective device.
1. A circuit, comprising:
a metal oxide semiconductor (MOS) device;
a protective device connected between the MOS device and an output voltage connection of the MOS device; and
gate protection circuitry configured to provide a bias voltage to a gate of the protective device, the bias voltage comprising a DC bias component and an AC bias component that synchronously varies with a voltage of the output voltage connection, wherein
the gate protection circuitry comprises a DC bias circuit comprising a resistor directly connected between a pair of current sources and the DC bias component is based upon a current level of the pair of current sources and a resistance of the resistor.
2. The circuit of claim 1 , wherein the AC bias component is an attenuated version of the voltage of the output voltage connection.
3. The circuit of claim 1 , wherein the gate protection circuitry comprises a voltage divider configured to provide the AC bias component.
4. The circuit of claim 3 , wherein the voltage divider comprises a resistance network including a plurality of resistors.
5. The circuit of claim 3 , wherein the DC bias circuit is configured to combine the AC bias component with the DC bias component.
6. The circuit of claim 5 , wherein the DC bias component is generated by the DC bias circuit.
7. The circuit of claim 1 , wherein the current level of the pair of current sources is programmable.
8. An integrated circuit (IC) chip comprising at least one of the circuit of claim 1 .
9. A circuit, comprising:
a metal oxide semiconductor (MOS) device;
a plurality of protective devices connected between the MOS device and an output voltage connection of the MOS device; and
gate protection circuitry configured to provide a plurality of bias voltages to the plurality of protective devices, each of the plurality of bias voltages provided to a gate of a corresponding one of the plurality of protective devices, each of the plurality of bias voltages comprising a DC bias component and an AC bias component that synchronously varies with a voltage of the output voltage connection.
10. The circuit of claim 9 , wherein the AC bias component of each of the plurality of bias voltages is a different attenuated version of the voltage of the output voltage connection.
11. The circuit of claim 9 , wherein the gate protection circuitry comprises a voltage divider configured to provide the AC bias component of each of the plurality of bias voltages.
12. The circuit of claim 11 , wherein the voltage divider comprises a resistance network including a plurality of resistors.
13. The circuit of claim 11 , wherein the gate protection circuitry further comprises a plurality of DC bias circuits, each of the plurality of DC bias circuits corresponding to one of the plurality of protective devices, each of the plurality of DC bias circuits configured to combine the AC bias component of the corresponding one of the plurality of protective devices with the DC bias component.
14. The circuit of claim 13 , wherein the DC bias component of each of the plurality of bias voltages is generated by a corresponding one of the plurality of DC bias circuits.
15. An integrated circuit (IC) chip comprising the circuit of claim 9 .
16. A method for protecting a metal oxide semiconductor (MOS) device, comprising:
attenuating an output voltage of an output connection corresponding to the MOS device to generate a plurality of attenuated output voltages, each of the plurality of attenuated output voltages corresponding to one of a series of protective devices electrically coupled between the MOS device and the output connection;
combining each of the plurality of attenuated output voltages with a constant offset voltage to generate a plurality of gate bias voltages, each of the plurality of gate bias voltages corresponding to one of the series of protective devices; and
providing each of the plurality of gate bias voltages to the corresponding one of the series of protective devices.
17. The method of claim 16 , wherein each of the plurality of attenuated output voltages is combined with a constant offset voltage associated with the corresponding one of the series of protective devices.
18. The method of claim 17 , further comprising generating the constant offset voltage associated with each corresponding one of the series of protective devices.