Device and method for preventing lost synchronization
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.
1. A method for preventing synchronization loss between a first node and a second node, comprising:
determining that synchronization between the first, node and the second node has been established;
determining a frequency difference between a first frequency of the first node and a second frequency of the second node; and
decreasing a gain parameter of a clock data recovery circuit (CDR) based on the frequency difference between the first node and the second node.
2. The method of claim 1 , wherein the determining that synchronization between the first node and the second node has been established comprises:
providing a synchronization character detection signal and a signal from a timer circuit to a synchronization establishment circuit, wherein synchronization between the first node and the second node is established when a character code line and synchronization data are detected within a predetermined detection time.
3. The method of claim 1 , further comprising maintaining an initial gain parameter of the CDR until synchronization is established between the first node and the second node, wherein the decreasing a gain parameter comprises:
providing a switching signal to a selector to set the gain of the CDR to an adjusted gain parameter, wherein the adjusted gain parameter is less than the initial gain parameter.
4. A device for preventing lost synchronization, the device comprising:
a synchronization establishment unit configured to determine that synchronization between a first node and a second node has been established;
a register configured to maintain an initial gain parameter of a clock data recovery (CDR) the second node are synchronized;
a conversion circuit configured to generate an adjusted gain parameter for the CDR circuit based on a frequency difference between the first node and the second node; and
a response sensitivity changing unit configured to switch a gain of the CDR from an initial gain parameter to the adjusted gain parameter after the first node and the second node are synchronized, wherein the adjusted pin parameter is less than the initial gain parameter.
5. The device according to claim 4 , further comprising:
a microcomputer; and
a notification unit configured to notify which notifies the microcomputer of an establishment notification signal indicating establishment of synchronization, wherein the microcomputer decreases the gain of the CDR in response to the establishment notification signal.
6. The device according to claim 5 , wherein:
the microcomputer rewrites the register to decrease the response sensitivity in response to the establishment notification signal.
7. The device according to claim 5 , wherein the notification unit includes an interrupt processor which generates the establishment notification signal as an interrupt signal provided to the microcomputer.