Chip instrumentation for in-situ clock domain characterization
Chip instrumentation determines, in-situ, an allowable increase over product specification in the operating frequency of at least one clock domain in an integrated circuit for a given set of environmental, power supply and/or functionality constraints. Information on the allowable increase in operating frequency for the at least one clock domain is provided to circuits and/or software to effect change in operating frequency.
1. A method of providing information indicative of an operating speed for a clock domain on a chip, comprising:
setting, on the chip, information that defines a test operating speed;
operating, at the test operating speed, a duplicate critical circuit path;
determining whether the duplicate critical circuit path produces an expected result when operated at the test operating speed;
changing, if the determination is affirmative, the information that defines the test operating speed to produce an increased test operating speed that is increased by a predetermined amount; and
setting, if the determination is negative, information that defines a real operating speed to be equal to the increased test operating speed minus the predetermined amount;
wherein the duplicate critical circuit path matches physical and electrical characteristics of an actual critical circuit path in the clock domain.
2. The method of claim 1 , further comprising:
subsequent to changing, determining whether the duplicate critical circuit path produces the expected result when operated at the test operating speed.
3. The method of claim 1 , further comprising:
subsequent to setting information that defines the real operating speed to be equal to the test operating speed minus the predetermined amount, storing the information.
4. The method of claim 3 , further comprising:
outputting the stored information indicative of the value of the real operating speed.
5. The method of claim 1 , further comprising:
selecting the duplicate critical circuit path from a plurality of duplicate critical circuit paths.
6. The method of claim 5 , wherein selecting the duplicate critical circuit path from the plurality of duplicate critical circuit paths comprises:
receiving, at the chip, information specifying which one of the plurality of duplicate critical circuit paths to select.
7. The method of claim 5 , wherein selecting the duplicate critical circuit path from the plurality of duplicate critical circuit paths comprises:
determining, at the chip, which one of a plurality of actual critical paths is in use by the chip.
8. A method of providing information indicative of an operating speed range on a chip, comprising:
operating speed characterization circuitry disposed on the chip;
determining, based at least in part on the operation of the speed characterization circuitry, a first operating speed for at least a portion of the chip, the first operating speed being different than a nominally specified operating speed;
generating information representative of the first operating speed; and
using the information in an on-chip clock generator to operate at least a portion of the chip at the first operating speed;
wherein operating the speed characterization circuitry includes operating a first ring oscillator to generate a first signal having a frequency predominantly dependent on a first electrical characteristic of the first ring oscillator, and operating a second ring oscillator to generate a second signal having a frequency predominantly dependent on a second electrical characteristic of the second ring oscillator.
9. The method of claim 8 , wherein generating the information representative of the first operating speed comprises accessing a table containing a mapping of ring oscillator frequencies to operating speeds.
10. An integrated circuit, comprising:
a clock domain;
a clock generator coupled to the clock domain and configured to generate a clock signal having a frequency; and
a speed test circuit configured to provide one or more outputs indicative of an operating speed range of the clock domain;
wherein the clock generator is configured to change the frequency of the clock signal based at least in part on the one or more outputs of the speed test circuit;
wherein the speed test circuit comprises:
a number N of ring oscillators;
an N:1 multiplexer coupled to an output signal of each of the N ring oscillators; and
a counter coupled to an output of the N:1 multiplexer;
wherein the N ring oscillators each generate a signal having a frequency indicative of the operating speed range of the clock domain;
wherein the counter is configured to be enabled for counting for a predetermined amount of time; and
wherein at least two of the N ring oscillators are configured to generate a signal having a frequency that is predominantly dependent on a different electrical parameter.
11. The integrated circuit of claim 10 , wherein the speed test circuit comprises a duplicate of a critical circuit path in the clock domain.
12. A method of providing information indicative of an operating speed for a clock domain on a chip, comprising:
setting, on the chip, information that defines a test operating speed;
operating, at the test operating speed, a duplicate critical circuit path;
determining whether the duplicate critical circuit path produces an expected result when operated at the test operating speed;
increasing, if the determination is affirmative, the test operating speed; and
decreasing, if the determination is negative, the test operating speed;
wherein the duplicate critical circuit path matches physical and electrical characteristics of an actual critical circuit path in the clock domain.