IP Library Granted Patent US 9,189,388
Granted Patent B2
US 9,189,388 · App. 13/927,881 · Granted Nov 17, 2015

Information processing apparatus

Inventors: Kazuki Makuni (Nagoya, JP); Takayuki Okinaga (Nagoya, JP); Shuichiro Azuma (Nagoya, JP); Yosuke Takata (Nagoya, JP); Noriaki Sugahara (Nagoya, JP)
Assignee: BUFFALO MEMORY CO., LTD.
G06F12/0246G06F2212/7208
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Quick Facts
Patent No.
US 9,189,388
App. No.
13/927,881
Granted
Nov 17, 2015
Kind
B2
Abstract

An information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus. The circuitry is configured to determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.

Claims (23)

1. An information processing apparatus, comprising:

a NAND type flash memory;

circuitry configured to control writing/reading of data to/from the NAND type flash memory; and

an interface configured to connect the information processing apparatus to a host apparatus, wherein

the circuitry is configured to

determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command is received from the host apparatus via the interface; and

erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.

2. The information processing apparatus of claim 1 , wherein the NAND type flash memory is divided into plural partitions.

3. The information processing apparatus of claim 2 , wherein each of the plural partitions is started at a head of the physical block.

4. The information processing apparatus of claim 3 , further comprising:

a storage medium configured to store the data to be overwritten upon receiving the overwrite command from the host apparatus.

5. The information processing apparatus of claim 4 , wherein the data to be overwritten is received from the host apparatus via the interface.

6. The information processing apparatus of claim 4 , wherein the circuitry is further configured to control the interface to transmit the data to be overwritten stored in the storage medium to the host apparatus when an instruction to read the data within the specific area is received from the host apparatus.

7. The information processing apparatus of claim 1 , further comprising:

a storage medium configured to store the data to be overwritten upon receiving the overwrite command from the host apparatus.

8. The information processing apparatus of claim 7 , wherein the data to be overwritten is received from the host apparatus via the interface.

9. The information processing apparatus of claim 7 , wherein the circuitry is further configured to control the interface to transmit the data to be overwritten stored in the storage medium to the host apparatus when an instruction to read the data within the specific area is received from the host apparatus.

10. An information processing method performed by an information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus, the method comprising:

determining, by the circuitry, whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command has been received from the host apparatus via the interface; and

erasing, by the circuitry, a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.

11. A non-transitory computer-readable medium including computer-program instructions, which when executed by an information processing apparatus including a NAND type flash memory; circuitry configured to control writing/reading of data to/from the NAND type flash memory; and an interface configured to connect the information processing apparatus to a host apparatus, cause the information processing apparatus to:

determine whether to erase data stored in a specific area within the NAND type flash memory by overwriting the data based on whether an overwrite command has been received from the host apparatus via the interface; and

erase a physical block including the specific area when it is determined to erase the data by removing electric charges in the NAND type flash memory in the physical block including the specific area.

Assignments (4)
CHANGE OF NAME Recorded Sep 30, 2025
From: MELCO HOLDINGS INC.
To: BUFFALO INC.
Reel/Frame 072988/0847 →
MERGER Recorded Jul 23, 2025
From: BUFFALO INC.
To: MELCO HOLDINGS INC.
Reel/Frame 072191/0806 →
MERGER Recorded Mar 14, 2018
From: BUFFALO MEMORY CO., LTD.
To: BUFFALO INC.
Reel/Frame 045600/0187 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2013
From: MAKUNI, KAZUKI; OKINAGA, TAKAYUKI; AZUMA, SHUICHIRO; TAKATA, YOSUKE; SUGAHARA, NORIAKI
To: BUFFALO MEMORY CO., LTD.
Reel/Frame 030692/0535 →
Priority Claims (1)
JP 2012-144642 · Jun 27, 2012 · national
Continuity (1)
Related Publication 20140006695A1 · Jan 2, 2014