Capacitance sensing circuits and methods

1. A capacitance sense system, comprising:

a capacitance sense input configured to receive an input signal that varies according to a sensed capacitance;

an integrator/discharge circuit configured to integrate the input signal and discharge the integrated input signal toward the reference level in conversion operations; and

a remainder retainer section configured to quantize the discharging of the integrated input signal, and retain any remainder of the integrated input signal that follows a quantization point for a next conversion by the integrator/discharge circuit.

2. The capacitance sense system of claim 1 , wherein:

the remainder retainer section includes

a comparator having a first input coupled to the integrator/discharge circuit, and configured to generate a comparator output signal that transitions in synchronism with a periodic signal, and

a current supply circuit configured to supply at least one reference current to the integrator circuit, and to disable the reference current in response to the comparator output signal.

3. The capacitance sense system of claim 1 , wherein:

the integrator/discharge circuit comprises

a first operational amplifier (op amp) having a first op amp input coupled to receive the input signal and a reference current from the remainder retainer section, and a second op amp input coupled to receive a reference voltage, and

first capacitor connections disposed between the first op amp input and an op amp output, and configured to accept a first integrating capacitance.

4. The capacitance sense system of claim 1 , wherein:

the integrator/discharge circuit comprises

a differential integrator having a first differential input coupled receive the input signal and a first reference current from the remainder retainer section, and a second differential input coupled to receive the input signal and a second reference current from the remainder retainer section;

first capacitor connections disposed between the first differential input and an integrator output, and configured to accept a first integrating capacitance, and

second capacitor connections disposed between the second differential input and integrator output, and configured to accept a second integrating capacitance.

5. The capacitance sense system of claim 1 , further including:

a demodulator section configured to demodulate an initial input signal with a time varying transmit signal to generate the input signal.

6. The capacitance sense system of claim 5 , wherein:

the demodulator section includes at least one switch coupled between a sense input and the integrator/discharge circuit that is enabled in response to a control signal that is synchronous with the transmit signal.

7. The capacitance sense system of claim 5 , wherein:

the integrator/discharge circuit includes first and second capacitor connections configured to connect to terminals of a capacitor; and

the demodulator section includes a switch network configured to connect the first capacitor connection to receive a reference current in response to a first timing signal having a first value, and connect the second capacitor connection to the receive the reference current in response to a first timing signal having a second value; wherein

the first timing signal is synchronous with the transmit signal.

8. The capacitance sense system of claim 5 , wherein:

the integrator/discharge circuit includes first and second differential inputs; and

the demodulator section includes a switch network configured to connect a first reference current to flow into the first differential input in response to a first timing signal having a first value, and connect a second reference current to flow from the second differential input in response to the first timing signal having a second value; wherein

the first timing signal is synchronous with the transmit signal.

9. A method, comprising:

integrating a capacitance sense input signal and discharging the integrated input signal toward a reference level with a reference current;

terminating the reference current when the integrated and discharged input signal is proximate the reference level;

generating an output value representing the time between the start of the integrating of the input signal and the terminating of the reference current; and

retaining any remainder arising from the terminating of the reference current for use for in a next integrating and discharging of the input signal; wherein

the remainder comprises a difference between the integrated and discharged input signal and the reference level.

10. The method of claim 9 , wherein:

discharging the integrated value includes generating a discharge current with a current source controlled by a comparison between the integrated and discharged input signal and the reference level.

11. The method of claim 9 , wherein:

terminating the reference current includes terminating the reference current according to a comparison between the integrated and discharged input signal and the reference level.

12. The method of claim 9 , further including:

generating the capacitance sense input signal by

driving at least one of a plurality of transmit electrodes of a sensor array with a time varying transmit signal, and

receiving a corresponding capacitance sense current on at least one of a plurality of receive electrodes of the sensor array; wherein

the transmit electrodes are disposed in a first direction and the receive electrodes are disposed in a second direction different from the first direction.

13. The method of claim 12 , wherein:

generating the capacitance sense input signal further includes demodulating the capacitance sense input signal with the transmit signal.

14. The method of claim 9 , further including:

the reference current is terminated synchronous to a reference clock signal, and the remainder includes any quantization error from such a termination; and

generating a count value from the output value by counting the duration of the output value according to a periodic signal that is the same as, or synchronous to, the reference clock signal.

15. The method of claim 9 , further including:

integrating the capacitance sense input signal includes

charging a first capacitance with the input signal in a first conversion, and

charging a second capacitance with the input signal in a second conversion following the first conversion; and

discharging the integrated input signal includes

applying a reference current that flows into the second capacitance in the first conversion, and

applying a reference current that flows from the first capacitance in the second conversion.

16. A method, comprising:

for each of a plurality of conversion operations

integrating a capacitance sense input signal and discharging the integrated input signal toward a reference level, and terminating the discharging of the integrated input signal in response to the integrated input signal being determined to be proximate a reference level;

generating an output value corresponding to the time between the start of the integrating of the input signal and the termination of the discharging of the integrated input signal; and

retaining any remainder in the conversion operation for inclusion in a subsequent conversion operation.

17. The method of claim 16 , further including:

generating the capacitance sense input signal by

inducing a current on one of a plurality of receive electrodes coupled to at least one transmit electrode that receives a time varying transmit signal.

18. The method of claim 16 , wherein:

integrating the input signal includes integrating the signal with an integrator operational amplifier (op amp) having an integrating capacitor in a feedback loop; and

discharging the integrated value includes applying a reference current to the integrating capacitor.

19. The method of claim 16 , wherein:

integrating the input signal includes applying the input signal to first or second differential inputs of a differential integrator according to a control signal synchronous with transmit signal.

20. The method of claim 16 , further including:

terminating the discharging of the integrated input signal in synchronism with a timing clock; and

generating a count value for each conversion according to a number of reference clock transitions during the output value; wherein

the reference clock is synchronous with the timing clock.