Electro-static discharge power supply clamp with disablement latch
View Patent ↗The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.
1. A circuit for protecting integrated circuitry comprising:
an integrated circuit including a power supply node and a common node;
a resistor coupled to the power supply node;
a capacitor coupled to the common node and further coupled to the resistor to form a first node;
a NOR circuit including a first NOR circuit input in communication with the first node, a NOR circuit output coupled to a second node, and a second NOR circuit input;
an inverter including an inverter input coupled to the second node, and an inverter output coupled to the second NOR circuit input to provide the second NOR circuit input with a logic state that is the same as an instantaneous logic state of the inverter output;
a NFET including a gate coupled to the second node, a drain coupled to the power supply node, and a source coupled to the common node.
2. The circuit for protecting integrated circuitry of claim 1 wherein the common node is a ground node of the integrated circuit.
3. The circuit for protecting integrated circuitry of claim 1 wherein the capacitor is a first capacitor, and the circuit further includes a second capacitor coupled between an output of the second inverter and the common node.