DIRECT SAMPLING RECEIVER WITH CONTINUOUS-TIME MDAC
Methods and apparatuses are described for a direct sampling receiver having high dynamic range and low noise figure with a continuous-time (CT) multiplying digital-to-analog converter (MDAC) architecture. In a multipath architecture, the input signal is sampled in the quantizer path, but not the CT signal path. In the CT signal path, only a filtered residue signal is sampled. Coarse bits generated in the quantizer path and fine bits generated in the input signal path are digitally combined to reconstruct the analog input signal in the digital domain. Filtering, aperture error control and digital equalization remove sources of errors, resulting in high performance. Advantages include toleration of multiple blocker signals, simultaneous reception of multiple weak channels and/or strong and weak channels, operation with simplified gain control and reduced pre-amplification as well as operation without excessive power consumption, external filters and tunable local oscillator (LO).
1 . A device comprising:
a first signal path configured to receive and sample an input signal and generate a coarse signal;
a second signal path configured to receive but not sample the input signal, subtract the coarse signal from the input signal in the analog domain to generate a residue signal and sample the residue signal to generate a fine signal; and
a digital combiner configured to combine the coarse and fine signals in the digital domain to generate an output signal.
2 . The device of claim 1 , wherein the first signal path comprises an M-bit analog-to-digital converter (ADC) to generate the coarse signal in the digital domain and an M-bit digital-to-analog converter (DAC) to generate the coarse signal in the analog domain.
3 . The device of claim 2 , wherein the first signal path further comprises a phase rotator to generate a variable sampling phase for the M-bit ADC, wherein the phase rotator is controlled by a phase tracking loop from the fine signal.
4 . The device of claim 1 , wherein the second signal path comprises an N-bit analog-to-digital converter (ADC) to generate the fine signal in the digital domain.
5 . The device of claim 4 , wherein the second signal path comprises an analog delay applied to the input signal before subtracting the coarse signal from the input signal.
6 . The device of claim 5 , wherein the second signal path comprises an amplifier configured to amplify the residue signal to generate an amplified residue signal.
7 . The device of claim 6 , wherein the amplifier gain is controlled by a gain control loop from the fine signal.
8 . The device of claim 7 , wherein the second signal path further comprises a filter configured to filter the amplified residue signal before the N-bit ADC sampling the amplified residue signal to generate the fine signal.
9 . The device of claim 8 , wherein the second signal path further comprises an equalizer to generate an equalized fine signal from the fine signal, the digital combiner configured to combine the coarse signal and equalized fine signal in the digital domain to generate the output signal.
10 . The device of claim 4 , wherein sampling rates of the M-bit ADC and the M-bit DAC are greater than a sampling rate of the N-bit ADC.
11 . The device of claim 1 , further comprising:
a pseudo random noise generator configured to generate a noise signal, the noise signal added to the coarse signal in the digital domain before conversion to the analog domain and subtraction from the input signal, the noise signal being removed by the digital combiner.
12 . The device of claim 11 , wherein the pseudo random noise generator is configured to generate a noise signal to calibrate the equalizer to compensate the amplitude and phase responses of the second signal path.
13 . A method comprising:
in a first signal path:
receiving and sampling an input signal in an M-bit analog-to-digital (ADC) converter to generate a coarse signal in the digital domain, and
converting the coarse signal in the digital domain to a coarse signal in the analog domain in an M-bit digital-to-analog converter (DAC); and
in a second signal communication path:
receiving but not sampling the input signal,
subtracting the coarse signal from the input signal in the analog domain to generate a residue signal, and
sampling the residue signal in an N-bit ADC to generate a fine signal; and
digitally combining the coarse and fine signals in the digital domain to generate an output signal.
14 . The method of claim 13 , further comprising:
tracking a phase from the fine signal and controlling a sampling phase of the M-bit ADC.
15 . The method of claim 13 , further comprising:
applying a delay to the input signal before subtracting the coarse signal from the input signal.
16 . The method of claim 15 , further comprising:
amplifying the residue signal to generate an amplified residue signal; and
controlling the amplifier gain by a gain control loop from the fine signal.
17 . The method of claim 16 , further comprising:
filtering the amplified residue signal, the N-bit ADC sampling the amplified residue signal to generate the fine signal.
18 . The method of claim 17 , further comprising:
generating, by an equalizer, an equalized fine signal from the fine signal, the digital combiner combining the coarse signal and equalized fine signal in the digital domain to generate the output signal.
19 . The method of claim 18 , further comprising:
calibrating the equalizer by adding a pseudo-noise signal to the coarse signal and
removing the pseudo-noise signal during the digital combination.
20 . A device comprising:
an analog-to-digital converter (ADC) that converts an analog signal into a plurality of bits, the ADC comprising:
a coarse ADC that samples the analog signal to generate a coarse bit in the plurality of bits;
a fine ADC that samples a residue of the analog signal instead of the analog signal to generate a fine bit in the plurality of bits; and
a digital combiner that combines the coarse and fine signals to generate a digital representation of the analog signal.