Method of scheduling threads for execution on multiple processors within an information handling system

1. A computer-implemented method of improving thread execution speed within a multi-processor system having at least a first processor and a second processor, each of the processors of the multi-processor system having a plurality of individual cores, the method comprising:

generating a plurality of threads to schedule for execution on the processors;

initially assigning at least one thread to a first processor for execution on a core of the first processor;

determining a core utilization rate for each of the other threads being scheduled;

identifying whether any of the other threads being scheduled has a core utilization rate greater than a pre-established core utilization rate threshold;

in response to identifying a specific other thread assigned to the first processor having a core utilization rate that is greater than the pre-established core utilization rate threshold, re-assigning execution of the specific other thread from the first processor to the second processor, whereby the re-assigned other thread is able to execute on the second processor at a greater execution rate than the pre-established core utilization rate threshold;

initially setting a timer to track an elapsed time since a thread count has been completed to identify threads being executed above the pre-established core utilization rate threshold;

sorting the other threads that have a core utilization rate greater than the pre-established core utilization rate threshold into pairs of a first thread and a second thread;

determining if any pair of threads remain to be assigned;

in response to there not being any pair of threads remaining to be assigned, determining if the timer has expired;

in response to expiration of the timer, re-counting the number of threads above the pre-established core utilization rate threshold; and

resetting and restarting the timer to track a next elapsed time.

2. The method of claim 1 , further comprising:

determining whether a specific processor has been pre-assigned to execute each of the first thread and the second thread; and

in response to neither of the first thread and the second thread being pre-assigned to execute on a specific one of the processors, assigning the first thread to execute on the first processor and assigning the second thread to execute on the second processor.

3. The method of claim 1 , further comprising:

sorting pairs of the other threads that have a core utilization rate greater than the pre-established core utilization rate threshold into pairs of a first thread and a second thread;

determining whether a specific one of the processors has been assigned to execute each of the first thread and the second thread; and

in response to the first thread being assigned to execute on the first processor and the second thread not being assigned to execute on a specific one of the processors, assigning the second thread to execute on the second processor.

4. The method of claim 1 , further comprising:

sorting the threads that have a core utilization rate greater than the pre-established core utilization rate threshold into pairs of a first thread and a second thread;

determining the processor assigned to execute each of the first thread and the second thread; and

in response to both the first and second threads being assigned to execute on the first processor, re-assigning the second thread to execute on the second processor.

5. The method of claim 1 , further comprising:

identifying at least one high priority process and at least one low priority process;

generating a first set of a low priority threads associated with the low priority process and a second set of high priority threads associated with the high priority process; and

assigning execution of the low priority threads to the first processor.

6. The method of claim 1 , further comprising:

ranking the threads based on the core utilization rate of each thread;

counting a number of threads;

determining if the counted number of threads are greater than the lower threshold number and less than an upper threshold number of threads; and

in response to the counted number of threads being greater than the lower threshold number and less than the upper threshold number:

arranging the threads having core utilization rates above the pre-established core utilization rate threshold into pairs of a first thread and a second thread; and

assigning execution of one of the first and second threads of each pair of threads to a different processor.

7. The method of claim 6 , further comprising:

in response to the counted number of threads being less than the upper threshold, maintaining the current processor assignments for the threads.

8. The method of claim 6 , further comprising:

in response to the counted number of threads being less than a pre-determined number of threads, assigning the threads above the pre-established core utilization rate threshold to execute on the first processor.

9. The method of claim 6 , wherein ranking the threads further comprises:

sorting the threads based on increasing core utilization rates into an ordered set of threads from a lowest core utilization rate to a highest core utilization rate.

10. An information handling system (IHS) comprising:

a multi-processor system including a plurality of processors, each of the processors having a plurality of cores;

a memory coupled to the processors via a system interconnect;

a first processor having firmware executing thereon to improve thread execution speed within the multi-processor system, wherein the firmware configures the first processor to:

generate a plurality of threads to schedule for execution on the processors;

initially assign at least one thread to a first processor for execution on a core of the first processor;

determine a core utilization rate for each of the other threads being scheduled;

identify whether any of the other threads being scheduled has a core utilization rate greater than a pre-established core utilization rate threshold;

in response to identifying a specific thread executing on the first processor having a core utilization rate that is greater than the pre-established core utilization rate threshold, re-assign execution of the specific thread from the first processor to the second processor, whereby the re-assigned thread is able to execute on the second processor at a greater execution rate than the pre-established core utilization rate threshold;

initially set a timer to track an elapsed time since a thread count has been completed to identify threads being executed above the pre-established core utilization rate threshold;

sort the other threads that have a core utilization rate greater than the pre-established core utilization rate threshold into pairs of a first thread and a second thread;

determine if any pair of threads remain to be assigned;

in response to there not being any pair of threads remaining to be assigned, determine if the timer has expired;

in response to expiration of the timer, re-count the number of threads above the pre-established core utilization rate threshold; and

reset and restart the timer to track a next elapsed time.

11. The information handling system of claim 10 , wherein the firmware further configures the first processor to:

determine whether a specific processor has been pre-assigned to execute each of the first thread and the second thread; and

in response to neither of the first thread and the second thread being pre-assigned to execute on a specific one of the processors, assign the first thread to execute on the first processor and assign the second thread to execute on the second processor.

12. The information handling system of claim 10 , wherein the firmware further configures the first processor to:

sort the other threads that have a core utilization rate greater than the pre-established core utilization rate threshold into pairs of a first thread and a second thread;

determine whether a specific one of the processors has been assigned to execute each of the first thread and the second thread; and

in response to the first thread being assigned to execute on the first processor and the second thread not being assigned to execute on a specific one of the processors, assign the second thread to execute on the second processor.

13. The information handling system of claim 10 , wherein the firmware further configures the first processor to:

sort the other threads that have a core utilization rate greater than the pre-established core utilization rate threshold into pairs of a first thread and a second thread;

determine the processor assigned to execute each of the first thread and the second thread; and

in response to both the first and second threads being assigned to execute on the first processor, re-assign the second thread to execute on the second processor.

14. The information handling system of claim 10 , wherein the firmware further configures the first processor to:

identify at least one high priority process and at least one low priority process;

generate a first set of a low priority threads associated with the low priority process and a second set of high priority threads associated with the high priority process;

assign execution of the low priority threads to the first processor.

15. The information handling system of claim 10 , wherein the firmware further configures the first processor to:

rank the threads based on the core utilization rate of each thread;

count a number of threads;

determine if the counted number of threads are greater than the lower threshold and less than an upper threshold number of threads; and

in response to the counted number of threads being greater than the lower threshold and less than the upper threshold:

arrange the threads having core utilization rates above the pre-established core utilization rate threshold into pairs of a first thread and a second thread; and

assign execution of one of the first and second threads of each pair of threads to a different processor.

16. The information handling system of claim 15 , wherein the firmware further configures the first processor to:

in response to the counted number of threads being less than the upper threshold, maintain the current processor assignments for the threads.

17. The information handling system of claim 15 , wherein the firmware further configures the first processor to:

in response to the counted number of threads being less than a pre-determined number of threads, assign the threads above the pre-established core utilization rate threshold to execute on the first processor.

18. The information handling system of claim 15 , wherein the firmware further configures the first processor to:

sort the threads based on increasing core utilization rates into an ordered set of threads from a lowest core utilization rate to a highest core utilization rate.