Method and apparatus for multiplexing ethernet channels
View Patent ↗One embodiment of the present invention provides a system that facilitates multiplexing low-speed Ethernet channels onto a high-speed channel. During operation, the system receives a number of low-speed Ethernet channels. Next, the system derives N bit streams from the number of low-speed Ethernet channels, and feeds each bit stream to an input of a serializer, which is conventionally used to serialize bits from a single channel. Each input of the serializer comprises one bit of an N-bit-wide parallel input bus, and the data rate of the serializer output matches the data rate of the high-speed channel. The system then transmits the output of the serializer onto the high-speed channel.
1. A method for bit-level demultiplexing a high-speed channel, comprising:
receiving a serial bit stream from the high-speed channel;
generating a plurality of bit streams from the serial bit stream, wherein the plurality of bit streams correspond to a marked channel and a plurality of unmarked channels; and
if ten low-speed Ethernet channels are to be transmitted, producing the ten low-speed Ethernet channels by aligning the unmarked channels based upon their respective positions with regard to the marked channel.
2. The method of claim 1 , further comprising:
sending the plurality of bit streams to a decoder, wherein the decoder is configured to detect a special bit pattern marking the marked channel.
3. The method of claim 2 , wherein the special bit pattern comprises a plurality of characters corresponding to a combination of logical zeros and logical ones.
4. The method of claim 2 , wherein the special bit pattern comprises a plurality of proprietary idle characters.
5. The method of claim 1 , further comprising:
if eight low-speed Ethernet channels are to be transmitted, sending the plurality of bit streams to a decoder to obtain the eight low-speed Ethernet channels.
6. The method of claim 5 , further comprising:
decoding a ten parallel bit word into an eight parallel bit word.
7. The method of claim 1 ,
wherein the low-speed Ethernet channels are 125 MHz Ethernet channels; and
wherein the high-speed channel has a data rate of 1.25 GHz.
8. The method of claim 1 , further comprising:
if the ten low-speed Ethernet channels are to be transmitted:
obtaining ten bit streams from the serial bit stream, and
decoding the ten bit streams to detect a special bit pattern marking the marked channel in the ten low-speed Ethernet channels, wherein the other nine channels in the ten low-speed Ethernet channels comprise the unmarked channels.
9. An apparatus for bit-level demultiplexing a high-speed channel, comprising:
a receiving mechanism configured to receive a serial bit stream from the high-speed channel;
a deserializer configured to generate a plurality of bit streams from the serial bit stream, wherein the plurality of bit streams correspond to a marked channel and a plurality of unmarked channels; and
an alignment circuit configured to produce ten low-speed Ethernet channels by aligning the unmarked channels based upon their respective positions with regard to the marked channel.
10. The apparatus of claim 9 , further comprising:
a decoding circuit configured to detect a special bit pattern marking the marked channel.
11. The apparatus of claim 10 , wherein the special bit pattern comprises a plurality of characters corresponding to a combination of logical zeros and logical ones.
12. The apparatus of claim 10 , wherein the special bit pattern comprises characters which do not occur in 4B/5B encoding.
13. The apparatus of claim 10 , wherein the special bit pattern comprises a plurality of proprietary idle characters.
14. The apparatus of claim 9 , further comprising:
a 10B/8B decoder configured to obtain eight low-speed Ethernet channels from the plurality of bit streams.
15. The apparatus of claim 14 , wherein the 10B/8B decoder is configured to decode every ten parallel bit word into an eight parallel bit word.
16. The apparatus of claim 9 ,
wherein the low-speed Ethernet channels are 125 MHz Ethernet channels; and
wherein the high-speed channel has a data rate of 1.25 GHz.
17. An apparatus for bit-level demultiplexing a high-speed channel, comprising:
a deserializer configured to generate a plurality of bit streams from a serial bit stream received from the high-speed channel, wherein the plurality of bit streams correspond to a marked channel and a plurality of unmarked channels;
a 10B/8B decoder configured to obtain eight low-speed Ethernet channels from the plurality of bit streams; and
an alignment circuit configured to produce ten low-speed Ethernet channels by aligning the unmarked channels based upon their respective positions with regard to the marked channel.
18. The apparatus of claim 17 , further comprising:
a decoding circuit configured to detect a special bit pattern marking the marked channel.
19. The apparatus of claim 17 , further comprising:
a receiving circuit configured to receive the serial bit stream from the high-speed channel.
20. The apparatus of claim 17 ,
wherein the low-speed Ethernet channels are 125 MHz Ethernet channels; and
wherein the high-speed channel has a data rate of 1.25 GHz.