Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.
1. A semiconductor device comprising:
a first recess formed in a semiconductor substrate;
a second recess and a third recess formed in the semiconductor substrate and penetrating the first recess;
a first gate pattern formed over the second recess;
a second gate pattern formed over the third recess; and
a first insulation film and a second insulation film disposed on first and second sides of each of the first and second gate patterns,
wherein a thickness of the first insulation film is different from a thickness of the second insulation film.
2. The semiconductor device according to claim 1 , wherein a thickness of the insulation film pattern formed over the semiconductor substrate coupled to a storage node contact plug is greater than a thickness of the insulation film pattern formed over the semiconductor substrate coupled to a bit line contact plug.
3. The semiconductor device according to claim 2 , wherein a portion of the semiconductor substrate coupled to the storage node contact plug is formed to be at a higher level than a portion of the semiconductor substrate coupled to the bit line contact plug.
4. A semiconductor device comprising:
a first recess formed in a substrate;
a plurality of second recesses formed in the substrate and penetrating the first recess;
a gate formed over one of the plurality of second recesses;
a first junction region in the substrate on a first side of the gate and a second junction region in the substrate on a second side of the gate;
a first insulation film disposed over the substrate and provided between the gate and the first junction region; and
a second insulation film disposed over the substrate and provided between the gate and the second junction region,
wherein a portion of the second insulation film disposed towards outer edges of the first recess has a first thickness, and
wherein a portion of the first insulation film disposed between the second recesses has a second thickness that is less than the first thickness.
5. The semiconductor device of claim 4 , wherein the first and the second junction regions have a step difference from each other.
6. The semiconductor device of claim 4 , wherein a portion of the substrate coupled to the first junction region has a step difference from a portion of the substrate coupled to the second junction region.
7. The semiconductor device of claim 4 , wherein the first junction region is configured to have a relatively higher potential of gate induced drain leakage (GIDL) value than the second junction region.
8. The semiconductor device of claim 4 , wherein the first junction region is coupled to a storage node and the second junction region is coupled to a bit line.
9. The semiconductor device of claim 4 , wherein the vertical gate is a recess gate or a buried gate.
10. The semiconductor device of claim 4 , the device further comprising:
a third insulation film extending from the first insulation film upward along a first sidewall of the gate,
wherein the third insulation film is thinner than the first insulation film.
11. The semiconductor device of claim 4 , the device further comprising:
a fourth insulation film extending from the second insulation film upward along a second sidewall of the gate,
wherein the fourth insulation film is formed to substantially the same thickness as the second insulation film.
12. A semiconductor device comprising:
a semiconductor substrate;
a shallow recess in the semiconductor substrate;
first and second recesses penetrating the shallow recess;
a first gate in the first recess;
a second gate in the second recess;
a first insulation film disposed over surfaces of the shallow recess; and
a second insulation film disposed over sidewalls of the first and second recesses,
wherein a portion of the first insulation film disposed towards outer edges of the shallow recess has a first thickness, and
wherein a portion of the first insulation film disposed between the first and second recesses has a second thickness that is less than the first thickness.
13. The semiconductor device of claim 1 , wherein a portion of the second insulation film is disposed over the portion of the first insulation film disposed towards outer edges of the first recess.