IP Library Granted Patent US 9,542,261
Granted Patent B2
US 9,542,261 · App. 13/933,105 · Granted Jan 10, 2017

Methods, systems, and computer readable media for multi-packet cyclic redundancy check engine

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Quick Facts
Patent No.
US 9,542,261
App. No.
13/933,105
Granted
Jan 10, 2017
Kind
B2
Abstract

Methods, systems, and computer readable media for a multi-packet CRC engine are disclosed. According to one aspect, the subject matter described herein includes a system for a multi-packet CRC engine. The system includes an input module for receiving set of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits, multiple CRC pre-calculation blocks (CPBs) that receive from the input module subsets of the set of bits, each subset containing a portion of a packet less than all of a packet, and calculate a CRC value for its respective subset of bits, and an output module for receiving the calculated CRC values from the CPBs and using the calculated CRC values to produce packet-specific CRC values, where the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values.

Claims (36)

1. A system for performing a multi-packet cyclic redundancy check (CRC), the system comprising:

an input module for receiving a plurality of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits;

a plurality of CRC pre-calculation blocks (CPBs), wherein each CPB receives from the input module a subset of the plurality or bits, each subset containing a portion of a packet less than all of a packet, and calculates a CRC value for its respective subset of bits; and

an output module for receiving the calculated CRC values from the plurality of CPBs and using the calculated CRC values to produce packet-specific CRC values, wherein the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values and wherein the output module receives information about the locations of the packet boundaries from the input module and reconfigures internal data paths of the output module to direct data within a given set of packet boundaries to be combined with other data from within the same set of packet boundaries;

wherein the output module comprises a number of instances of duplicated components, and wherein each instance of duplicated components comprises a same number of select blocks and a same number of XOR circuits; and

wherein the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values by virtue of dynamically controlling the select blocks of the instances of duplicated components.

2. The system of claim 1 wherein the output module inserts the packet-specific CRC values into each of the corresponding at least one data packet.

3. The system of claim 1 wherein each of the CPBs calculates a CRC value using a pipelined architecture.

4. The system of claim 1 wherein each of the CPBs calculates a CRC value using a cascading, hierarchical combinatorial logic structure.

5. The system of claim 1 wherein the output module configures logic circuits within the output module according to the identified packet boundaries.

6. A method for performing a multi-packet cyclic redundancy check (CRC), the method comprising:

at an entity having hardware for processing network packets:

receiving a plurality of bits associated with at least one data packet;

identifying packet boundaries within the plurality of bits;

dividing the plurality of bits into a plurality of subsets of bits, each subset containing a portion of a packet less than all of a packet;

calculating a CRC value for each of the plurality of subsets of bits; and

combining the calculated CRC values according to identified packet boundaries to produce packet-specific CRC values, wherein combining the calculated CRC values according to the identified packet boundaries comprises receiving, at an output module, information about the locations of the packet boundaries from an input module and reconfiguring internal data paths of the output module to direct data within a given set of packet boundaries to be combined with other data from within the same set of packet boundaries;

wherein the output module comprises a number of instances of duplicated components, and wherein each instance of duplicated components comprises a same number of select blocks and a same number of XOR circuits; and

wherein reconfiguring internal data paths of the output module to direct data within a given set of packet boundaries to be combined with other data from within the same set of packet boundaries comprises dynamically controlling the select blocks of the instances of duplicated components.

7. The method of claim 6 comprising inserting the packet-specific CRC values into the corresponding packets.

8. The method of claim 6 wherein calculating a CRC value for each of the plurality of subsets of bits comprises using a pipelined architecture.

9. The method of claim 6 wherein calculating a CRC value for each of the plurality of subsets of bits comprises using a cascading, hierarchical combinatorial logic structure.

10. The method of claim 6 wherein combining the calculated CRC values according to identified packet boundaries to produce packet-specific CRC values comprises using the output module, which dynamically configures the data paths and logic circuits within the output module according to the identified packet boundaries to produce the packet-specific CRC values.

11. A non-transitory computer readable medium having stored thereon executable instructions that when executed by the processor of a computer control the computer to perform steps comprising:

at an entity for generating network packets and having hardware:

receiving a plurality of bits associated with at least one data packet;

identifying packet boundaries within the plurality of bits;

dividing the plurality of bits into a plurality of subsets of bits, each subset containing a portion of a packet less than all of a packet;

calculating a CRC value for each of the plurality of subsets of bits; and

combining the calculated CRC values according to identified packet boundaries to produce packet-specific CRC values, wherein combining the calculated CRC values according to the identified packet boundaries comprises receiving, at an output module, information about the locations of the packet boundaries from an input module and reconfiguring internal data paths of the output module to direct data within a given set of packet boundaries to be combined with other data from within the same set of packet boundaries;

wherein the output module comprises a number of instances of duplicated components, and wherein each instance of duplicated components comprises a same number of select blocks and a same number of XOR circuits; and

wherein reconfiguring internal data paths of the output module to direct data within a given set of packet boundaries to be combined with other data from within the same set of packet boundaries comprises dynamically controlling the select blocks of the instances of duplicated components.

12. The non-transitory computer readable medium of claim 11 for performing steps comprising inserting the packet-specific CRC values into the corresponding packets.

13. The non-transitory computer readable medium of claim 11 wherein calculating a CRC value for each of the plurality of subsets of bits comprises using a pipelined architecture.

14. The non-transitory computer readable medium of claim 11 wherein calculating a CRC value for each of the plurality of subsets of bits comprises using a cascading, hierarchical combinatorial logic structure.

15. The non-transitory computer readable medium of claim 11 wherein combining the calculated CRC values according to identified packet boundaries to produce packet-specific CRC values comprises using the output module, which dynamically configures the data paths and logic circuits within the output module according to the identified packet boundaries to produce the packet-specific CRC values.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2018
From: KEYSIGHT TECHNOLOGIES SINGAPORE (HOLDINGS) PTE. LTD.
To: KEYSIGHT TECHNOLOGIES SINGAPORE (SALES) PTE. LTD.
Reel/Frame 048225/0065 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2017
From: IXIA
To: KEYSIGHT TECHNOLOGIES SINGAPORE (HOLDINGS) PTE. LTD.
Reel/Frame 044222/0695 →
RELEASE OF SECURITY INTEREST Recorded Apr 26, 2017
From: SILICON VALLEY BANK, AS SUCCESSOR ADMINISTRATIVE AGENT
To: IXIA
Reel/Frame 042335/0465 →
SECURITY INTEREST Recorded Mar 3, 2015
From: IXIA; ANUE SYSTEMS, INC.; BREAKINGPOINT SYSTEMS, INC.
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 035121/0860 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2013
From: PEPPER, GERALD RAYMOND; WILSON, BRIAN ADAM
To: IXIA
Reel/Frame 031316/0282 →