Metamaterial power amplifier systems
View Patent ↗Power amplifying systems and modules and components therein are designed based on CRLH structures, providing high efficiency and linearity.
1. A bias circuit for biasing a transistor, comprising:
a first transmission line (“TL”) having a first end and a second end;
a second TL having a third end and a fourth end;
a third TL comprising a composite right and left handed (“CRLH”) structure and having a fifth end and a sixth end; wherein
the first TL, the second TL and the third TL are coupled radially to form a common portion with the first end, third end and the fifth end;
the first TL is configured to receive a bias signal from an external supply through the second end; and
the second TL is configured to send the bias signal to an RF signal path through the fourth end to bias the transistor coupled to the RF signal path.
2. The bias circuit as in claim 1 , wherein
the second TL and the third TL are configured to have a second phase response and a third phase response, respectively, to provide an open circuit at the fourth end of the second TL for signals in a plurality of frequency bands.
3. The bias circuit as in claim 2 , wherein
the second TL is configured to have the second phase response to provide arbitrary impedances at the common portion for the signals in the plurality of frequency bands; and
the third TL is configured based on the CRLH structure to have the third phase response to compensate for the arbitrary impedances.
4. The bias circuit as in claim 3 , wherein
the second phase response provides phases for the plurality of frequency bands chosen from k×180°, where k=0, ±1, ±2 . . . , between the fourth end and the sixth end to compensate for the arbitrary impedances to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is open; and
the third phase response provides phases for the plurality of frequency bands chosen from k×90°, where k=0, ±1, ±2 . . . , between the fourth end and the sixth end to compensate for the arbitrary phases to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is shorted.
5. The bias circuit of claim 1 , wherein the second TL has a plurality of phase responses.
6. The bias circuit of claim 1 , wherein the third TL has a plurality of phase responses.
7. The bias circuit of claim 1 , wherein the second TL is configured to provide an open circuit at the fourth end to signals in a plurality of frequency bands.
8. The bias circuit of claim 3 , wherein
the second phase response provides phases for the plurality of frequency bands chosen from k×2x°, where k=0, ±1, ±2 . . . , between the fourth end and the sixth end to compensate for the arbitrary impedances to have an open circuit at the fourth end to the plurality of frequency bands when the sixth end is open; and
the third phase response provides phases for the plurality of frequency bands chosen from k×x°, where k=0, ±1, ±2 . . . , between the fourth end and the sixth end to compensate for the arbitrary phases to have an open circuit at the fourth end to the plurality of frequency bands when the sixth end is shorted;
wherein x represents an angle.
9. A method for operating a bias circuit for biasing a transistor, the bias circuit comprising a first TL having a first end and a second end, a second TL having a third end and a fourth end, a third TL comprising a CRLH structure and having a fifth end and a sixth end, wherein the first TL, the second TL and the third TL are coupled radially to form a common portion with the first end, third end and the fifth end, the method comprising:
receiving, at the first TL, a bias signal from an external supply through the second end; and
sending, from the second TL, the bias signal to an RF signal path through the fourth end to bias the transistor coupled to the RF signal path.
10. The method of claim 9 , wherein the second TL has a plurality of phase responses.
11. The method of claim 9 , wherein the third TL has a plurality of phase responses.
12. The method of claim 9 , further comprising providing, at the fourth end of the second TL, an open circuit in response to signals in a plurality of frequency bands.
13. The method of claim 9 , wherein the second TL and the third TL are configured to have a second phase response and a third phase response, respectively, the method further comprising providing an open circuit at the fourth end of the second TL to signals in a plurality of frequency bands.
14. The method as in claim 13 , wherein:
the second TL has the second phase response to provide arbitrary impedances at the common portion for the signals in the plurality of frequency bands; and
the third TL has, based on the CRLH structure, the third phase response to compensate for the arbitrary impedances.
15. The method as in claim 13 , wherein:
the second phase response provides phases for the plurality of frequency bands chosen from k×2x°, where k=0, ±1, ±2 . . . , between the fourth end and the sixth end to compensate for the arbitrary impedances to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is open; and
the third phase response provides phases for the plurality of frequency bands chosen from k×x°, where k=0, ±1, ±2 . . . , between the fourth end and the sixth end to compensate for the arbitrary phases to have an open circuit at the fourth end for the plurality of frequency bands when the sixth end is shorted;
wherein x is an angle.
16. The method of claim 13 , wherein x=90 degrees.
17. A bias circuit for biasing a transistor, comprising:
a first transmission line (“TL”) having a first end and a second end;
a second TL having a third end and a fourth end;
means for providing multiple phase responses, said means for providing having a fifth end and a sixth end; wherein
the first TL, the second TL and the means for providing are coupled radially to form a common portion with the first end, third end and the fifth end;
the first TL is configured to receive a bias signal from an external supply through the second end; and
the second TL is configured to send the bias signal to an RF signal path through the fourth end to bias the transistor coupled to the RF signal path.
18. The bias circuit of claim 17 , wherein the second TL has a plurality of phase responses.
19. The bias circuit of claim 17 , wherein the second TL is configured to provide an open circuit at the fourth end to signals in a plurality of frequency bands.
20. The bias circuit of claim 17 , wherein the second TL is configured to provide an open circuit at the fourth end to signals in a plurality of frequency bands.