Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
View Patent ↗A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
1. A memory interface circuit configured to communicate with a processing unit and at least two different types of memory chips, comprising:
a first terminal configured to receive a control output signals from the processing unit to access at least one of the memory chips;
a conversion unit configured to covert the control output signals to memory input signals according to operation specifications of the memory chips;
a second terminal configured to connect to the memory chips via a common line, the common line being shared by the memory chips, and configured to output a write enable signal as one of the memory input signals through the common line; and
a third terminal configured to connect to one of the memory chips via a signal line, the signal line being different from the common line, and configured to output a chip enable signal as one of the memory input signals through the signal line,
wherein the conversion unit is configured to output one of the memory input signals to one of the memory chips according to one of the operation specifications of the one of many of the memory chips during a period from a time when the conversion unit outputs another one of the memory input signals to another one of the memory chips to a time when the conversion unit receives a memory output signal corresponding to the another one of the memory inputs signals from the another one of the memory chips.
2. The memory interface circuit according to claim 1 ,
wherein the at least two different types of memory chips include a synchronous dynamic random access memory and a flash memory.
3. The memory interface circuit according to claim 1 ,
wherein the at least two different types of memory chips include a static random access memory and a flash memory.
4. The memory interface circuit according to claim 1 , further comprising:
a register unit for storing the operation specifications of the memory chips.
5. The memory interface circuit according to claim 1 ,
wherein the memory input signals includes an address, a command and data.
6. The memory interface circuit according to claim 1 ,
wherein the memory input signals further includes a direct memory access control signal.
7. A memory interface circuit configured to communicate with a processing unit and at least two different types of memory chips comprising:
a first terminal configured to receive control output signals from the processing unit to access at least one of the memory chip;
a conversion unit configured to convert the control output signals to memory input signals according to operation specifications of the memory chips;
a second terminal configured to connect to the memory chips via a common line, the common line being shared by the memory chips, and configured to output a write enable signal as one of the memory inputs signals through the common line; and
a third terminal configured to connect to one of the memory chips via a signal line, the signal line being different from the common line, and configured to output a chip enable signal as one of the memory input signals through the signal line,
wherein the conversion unit is configured to output one of the memory input signals to one of the memory chips according to one of the operation specifications of the one of the memory chips and to receive a memory output signal corresponding to the one of the memory input signals from the one of the memory chips during a period from a time when the conversion unit outputs another one of the memory input signals to another one of the memory chips to a time when the conversion unit receives a memory output signal corresponding to the another one of the memory input signals from the another one of the memory chips.
8. The memory interface circuit according to claim 7 ,
wherein the at least two different typos of memory chips include a synchronous dynamic random access memory and a flash memory.
9. The memory interface according to claim 7 ,
wherein the at least two different types of memory chips include a static random access memory and a flash memory.
10. The memory interface circuit according to claim 7 , further comprising:
a register unit configured to store the operation specifications of the memory chips.
11. The memory interface circuit according to claim 7 ,
wherein the memory input signals includes an address, a command and data.
12. The memory interface circuit according to claim 7 ,
wherein the memory input signals further includes a direct memory access control signal.
13. A memory interface circuit configured to communicate with a processing unit and at least two different types of memory chips, comprising:
a first terminal configured to receive control output signals from the processing unit to access at least one of the memory chips;
a conversion unit configured to convert the control output signals to memory input signals according to operation specifications of the memory chips;
a second terminal configured to connect to the memory chips via a common line, the common line being shared by the memory chips, and configured to output a write enable signal as one of the memory input signals through the common line;
a third terminal configured to connect to one of the memory chips via a signal line, the signal line being different from the common line, and configured to output a chip enable signal as one of the memory input signals though the signal line; and
a signal holding unit configured to hold memory output signals,
wherein the memory interface circuit is configured to receive the memory output signals from the one of the memory chips, and
the conversion unit instructs the signal holding unit to temporarily hold the memory output signals when the processing unit is busy and instructs the signal holding unit to output the memory output signals held in the signal holding unit to the processing unit when the processing unit is ready.
14. The memory interface circuit according to claim 13 ,
wherein, when the processing unit is ready and the memory interface circuit receives the memory output signal from the one of the memory chips, the conversion unit instructs without holding the received memory output signals the signal holding unit to output the received memory output signals to the processing unit.
15. The memory interface circuit according to claim 13 ,
wherein the at least two different types of memory chips include a synchronous dynamic random access memory and a flash memory.
16. The memory interface circuit according to claim 13 ,
wherein the at least two different types of memory chips include a static random access memory and a flash memory.
17. The memory interface circuit according to claim 13 , further comprising:
a register unit configured to store the operation specifications of the memory chips.
18. The memory interface circuit according to claim 13 ,
wherein the memory input signals includes an address, a command and data.
19. The memory interface circuit according to claim 13 ,
wherein the memory inputs signals further includes a direct memory access control signal.
20. A memory interface circuit configured to communication with a processing unit and at least two different types of memory chips, comprising:
a first terminal configured to receive control output signals from the processing unit to access at least one of the memory chips;
a conversion unit configured to covert the control output signals to memory input signals according to operation specifications of the memory chips;
a second terminal configured to connect to the memory chips via a common line, the common line being shared by the memory chips, and configured to output a write enable signal as one of the memory input signals through the common line;
a third terminal configured to connect to one of the memory chips via a signal line, the signal line being different from the common line, and configured to output a chip enable signal as one of the memory input signals through the signal line;
an arbiter configured to output an instruction signal which indicates that requests of accesses to the one of the memory chips and another one of the memory chips are overlapped; and
a signal holding unit configured to hold at least one of the memory input signals in response to the instruction signal.
21. The memory interface circuit according to claim 20 ,
wherein the memory interface circuit is configured to receive memory output signals from the one of the memory chips, and
the conversion unit instructs the signal holding unit to temporarily hold the memory output signals when the processing unit is busy and instructs the signal holding unit to output the memory output signals held in the signal holding unit to the processing unit when the processing unit is ready.
22. The memory interface circuit according to claim 20 ,
wherein the at least two different types of memory chips include a synchronous dynamic random access memory and a flash memory.
23. The memory interface circuit according to claim 20 ,
wherein the at least two different types of memory chips include a static random access memory and a flash memory.
24. The memory interface circuit according to claim 20 , further comprising:
a register unit configured to store the operation specifications of the memory chips.
25. The memory interface circuit according to claim 20 ,
wherein the memory input signals includes an address, a command and data.
26. The memory interface circuit according to claim 20 ,
wherein the memory input signals further includes a direct memory access control signal.