SPAC series programmable array of capacitors
View Patent ↗A tunable series resonant circuit includes a voltage source, a source impedance, a variable capacitor, a series inductor, and a load impedance. The variable capacitor includes a sPAC (series programmable array of capacitors) having desirable characteristics for a tunable series resonant circuit. The sPAC may be a binary weighted sPAC, a thermometer coded sPAC, or some other sPAC.
1. A sPAC (series programmable array of capacitors) circuit comprising:
a first capacitor;
a second capacitor in series with the first capacitor, wherein the second capacitor has approximately half of a capacitance of the first capacitor;
a first switch in parallel with the first capacitor; and
a second switch in parallel with the second capacitor,
wherein the sPAC is a binary weighted sPAC.
2. The sPAC circuit of claim 1 , further comprising:
a first control node configured to control the first switch; and
a second control node configured to control the second switch.
3. The sPAC circuit of claim 1 , wherein the sPAC is configured to accept positive and negative control voltages.
4. The sPAC circuit of claim 3 , wherein the first switch is a DC (direct current) coupled stacked switch including at least two FETs (Field Effect Transistors).
5. The sPAC circuit of claim 1 , wherein the sPAC is not configured to accept negative control voltages.
6. The sPAC circuit of claim 5 , wherein the first switch is a single supply stacked FET (Field Effect Transistor).
7. The sPAC circuit of claim 6 , wherein the second switch has twice as many stacked FETs as the first switch has.
8. The sPAC circuit of claim 7 , further comprising a first coupling capacitor located in series between the first capacitor and the second capacitor.
9. The sPAC circuit of claim 8 , further comprising:
a third capacitor located in series with the second capacitor;
a third switch located in parallel with the third capacitor; and
a second coupling capacitor located in series between the second capacitor and the third capacitor.
10. The sPAC circuit of claim 9 , wherein the third capacitor has a capacitance of approximately one fourth of the first capacitor, and wherein the third switch has approximately four times as many stacked FETs as the first switch.
11. A sPAC (series programmable array of capacitors) circuit comprising:
a first capacitor;
a second capacitor in series with the first capacitor, wherein the second capacitor is approximately equal in capacitance to the first capacitor;
a first switch in parallel with the first capacitor; and
a second switch in parallel with the second capacitor,
wherein the sPAC is a thermometer coded sPAC.
12. A sPAC (series programmable array of capacitors) circuit comprising:
a first capacitor;
a second capacitor in series with the first capacitor;
a first switch in parallel with the first capacitor;
a second switch in parallel with the second capacitor;
a source impedance in series with the sPAC; and
a series inductor in series with the sPAC.
13. The sPAC circuit of claim 12 , further comprising:
a control portion configured to control the sPAC such that the sPAC circuit is matched to an external load.
14. The sPAC circuit of claim 12 , wherein the sPAC is a binary weighted sPAC, and wherein the second capacitor has approximately half of the capacitance of the first capacitor.
15. The sPAC circuit of claim 12 , wherein the sPAC is a thermometer coded sPAC, and wherein the second capacitor is approximately equal in capacitance to the first capacitor.
16. The sPAC circuit of claim 12 , wherein the sPAC is configured to accept positive and negative control voltages.
17. The sPAC circuit of claim 16 , wherein the first switch is a DC (direct current) coupled stacked switch including at least two FETs (Field Effect Transistors).
18. The sPAC circuit of claim 12 , wherein the sPAC is not configured to accept negative control voltages.
19. The sPAC circuit of claim 18 , wherein the first switch is a single supply stacked FET (Field Effect Transistor).
20. The sPAC circuit of claim 19 , wherein:
the sPAc is binary coded;
the second capacitor has about one half of the capacitance of the first capacitor.
21. The sPAC circuit of claim 20 , wherein the second switch has twice as many stacked FETs as the first switch has.
22. The sPAC circuit of claim 21 , further comprising a first coupling capacitor located in series between the first capacitor and the second capacitor.
23. The sPAC circuit of claim 22 , further comprising:
a third capacitor located in series with the second capacitor;
a third switch located in parallel with the third capacitor; and
a second coupling capacitor located in series between the second capacitor and the third capacitor.
24. The sPAC circuit of claim 23 , wherein the third capacitor has a capacitance of approximately one fourth of the first capacitor, and wherein the third switch has approximately four times as many stacked FETs as the first switch.