Method and system for providing a smart memory architecture

1. A method for providing a bit error rate built-in self test on a memory device, the method comprising:

entering a test mode;

internally generating, by the memory device, an error rate timing pattern;

performing, by the memory device, the bit error rate built-in self test based on the internally generated error rate timing pattern; and

measuring an error rate resulting from the bit error rate built-in self test;

wherein performing the bit error rate built-in self test further comprises:

receiving a mode register set command for a write error rate built-in self test;

entering the test mode responsive to receiving the mode register set command;

generating a next address;

resetting a memory value at the next address by writing a “0”;

updating a cycle count register;

determining whether or not a number of cycles based on the cycle count register has reached 1 e N , wherein N is a positive integer; and

in response to determining that the number of cycles has not reached 1 e N :

adjusting, based on the measured error rate, one or more test parameters; and

repeating the bit error rate built-in self test,

wherein repeating includes repeating the bit error rate built-in self test using the adjusted one or more test parameters.

2. The method of claim 1 , wherein performing the bit error rate built-in self test further comprises:

receiving the mode register set command for the write error rate built-in self test for write “1”s;

reading the memory value at the next address and verifying that the “0” was written;

determining whether the resetting of the memory value failed;

in response to determining that the resetting failed, updating a reset error count register;

in response to determining that the resetting did not fail:

writing the memory value at the next address with a “1”;

reading the memory value at the next address and verifying that the “1” was written;

determining whether the writing of the memory value at the next address with the “1” failed; and

in response to determining that the writing failed, updating a write error count register.

3. The method of claim 2 , wherein:

performing the bit error rate built-in self test includes performing a write error rate test;

measuring includes measuring a write error rate;

adjusting includes adjusting, based on the measured write error rate, the one or more test parameters; and

repeating includes repeating the write error rate test using the adjusted parameters.

4. The method of claim 2 , wherein:

performing the bit error rate built-in self test includes performing a read error rate test;

measuring includes measuring a read error rate;

adjusting includes adjusting, based on the measured read error rate, the one or more test parameters; and

repeating includes repeating the read error rate test using the adjusted parameters.

5. The method of claim 1 , wherein entering the test mode further comprises:

receiving one or more mode register set commands; and

entering the test mode responsive to the one or more mode register set commands.

6. The method of claim 1 , further comprising:

receiving one or more mode register set commands; and

configuring the one or more test parameters responsive to the one or more mode register set commands.

7. The method of claim 6 , wherein configuring the one or more test parameters further comprises:

setting at least one of a start voltage, a voltage range, and a voltage step.

8. The method of claim 6 , wherein configuring the one or more test parameters further comprises:

setting at least one of a test mode read pulse width and a test mode write pulse width.

9. The method of claim 1 , wherein adjusting the one or more test parameters further comprises:

automatically setting a read voltage to a next programmed voltage level.

10. The method of claim 1 , wherein adjusting the one or more test parameters further comprises:

automatically setting a write voltage to a next programmed voltage level.

11. The method of claim 1 , further comprising:

automatically re-assigning memory space within the memory device when the measured error rate exceeds a predefined threshold.

12. A method for providing a bit error rate built-in self test on a memory device, the method comprising:

performing, by the memory device, at least one of a write error rate built-in self test and a read error rate built-in self test; and

measuring an error rate resulting from at least one of the write error rate built-in self test and the read error rate built-in self test;

wherein performing the at least one of the write error rate built-in self test and the read error rate built-in self test further comprises:

receiving a mode register set command for the write error rate built-in self test;

entering a test mode responsive to receiving the mode register set command;

generating a next address;

resetting a memory value at the next address by writing a “0”;

updating a cycle count register;

determining whether or not a number of cycles based on the cycle count register has reached 1 e N , wherein N is a positive integer; and

in response to determining that the number of cycles has not reached 1 e N :

automatically adjusting, based on the measured error rate, one or more test parameters; and

repeating the at least one of the write error rate built-in self test and the read error rate built-in self test,

wherein repeating includes repeating the at least one of the write error rate built-in self test and the read error built-in self test using the adjusted one or more test parameters.

13. The method of claim 12 , wherein automatically adjusting further comprises:

automatically adjusting a voltage level for an address location responsive to the measured error rate.

14. The method of claim 12 , wherein automatically adjusting further comprises:

automatically adjusting a voltage level for an address segment responsive to the measured error rate.

15. The method of claim 12 , wherein automatically adjusting further comprises:

automatically adjusting a voltage level for an entire chip associated with the memory device responsive to the measured error rate.

16. The method of claim 12 , wherein automatically adjusting further comprises:

automatically adjusting a pulse width based on a next programmed test pulse width for an address location.

17. The method of claim 12 , wherein automatically adjusting further comprises:

automatically adjusting a pulse width based on a next programmed test pulse width for an address segment.

18. The method of claim 12 , wherein automatically adjusting further comprises:

automatically adjusting a pulse width based on a next programmed test pulse width for an entire chip associated with the memory device.

19. A memory device, comprising:

bit error rate control logic configured to control a bit error rate built-in self test;

an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;

a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test; and

a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test;

measuring an error rate resulting from at least one of the write error test pattern and the read error test pattern;

wherein the bit error rate control logic is configured to:

receive a mode register set command for the bit error rate built-in self test;

enter a test mode responsive to receiving the mode register set command;

generate a next address;

reset a memory value at the next address by writing a “0”;

update a cycle count register;

determine whether or not a number of cycles based on the cycle count register has reached 1 e N , wherein N is a positive integer; and

in response to determining that the number of cycles has not reached 1 e N :

automatically adjust, based on the measured error rate, one or more test parameters; and

repeat the bit error rate built-in self test using the adjusted one or more test parameters.

20. The memory device of claim 19 , further comprising:

logic configured to count cycles of the bit error rate built-in self test.

21. The memory device of claim 19 , further comprising:

a write error rate cycle count register configured to store a number of write cycles; and

a read error rate cycle count register configured to store a number of read cycles.

22. The memory device of claim 19 , further comprising:

a pulse width generator circuit; and

a pulse width register configured to provide code to select an intended pulse width delay in the pulse width generator circuit.

23. The memory device of claim 19 , further comprising:

a voltage generator; and

a voltage regulator register configured to produce a code to select a voltage bias level in the voltage generator.

24. The memory device of claim 23 , further comprising:

a write error counter configured to count a number of write errors of the bit error rate built-in self test; and

a read error counter configured to count a number of read errors of the bit error rate built-in self test.

25. A system for providing a bit error rate built-in self test, comprising:

a bus;

a memory coupled to the bus; and

a smart memory controller, including:

bit error rate control logic configured to control a bit error rate built-in self test;

an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;

a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test; and

a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test;

measuring an error rate resulting from at least one of the write error test pattern and the read error test pattern;

wherein the bit error rate control logic is configured to:

receive a mode register set command for the bit error rate built-in self test;

enter a test mode responsive to receiving the mode register set command;

generate a next address;

reset a memory value at the next address by writing a “0”;

update a cycle count register;

determine whether or not a number of cycles based on the cycle count register has reached 1 e N , wherein N is a positive integer; and

in response to determining that the number of cycles has not reached 1 e N :

automatically adjust, based on the measured error rate, one or more test parameters; and

repeat the bit error rate built-in self test using the adjusted one or more test parameters.

26. The system of claim 25 , wherein the smart memory controller further comprises:

logic configured to count cycles of the bit error rate built-in self test.

27. The system of claim 25 , wherein the smart memory controller further comprises:

a write error rate cycle count register configured to store a number of write cycles; and

a read error rate cycle count register configured to store a number of read cycles.

28. The system of claim 25 , wherein the smart memory controller further comprises:

a pulse width generator circuit; and

a pulse width register configured to provide code to select an intended pulse width delay in the pulse width generator circuit.

29. The system of claim 25 , wherein the smart memory controller further comprises:

a voltage generator; and

a voltage regulator register configured to produce a code to select a voltage bias level in the voltage generator.

30. The system of claim 29 , wherein the smart memory controller further comprises:

a write error counter configured to count a number of write errors of the bit error rate built-in self test; and

a read error counter configured to count a number of read errors of the bit error rate built-in self test.