IP Library Granted Patent US 9,478,670
Granted Patent B2
US 9,478,670 · App. 13/936,453 · Granted Oct 25, 2016

Non-volatile semiconductor storage device

Inventors: Masayuki Tanaka (Mie-ken, JP); Kenichiro Toratani (Kanagawa-ken, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
H01L29/792H01L21/28273H01L21/28282H01L27/11521H01L27/11568H01L29/4234H01L29/42324H01L29/7887H01L29/7923
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Quick Facts
Patent No.
US 9,478,670
App. No.
13/936,453
Granted
Oct 25, 2016
Kind
B2
Abstract

A non-volatile semiconductor storage device disclosed in the embodiment has a semiconductor substrate, a first insulating film, a first charge storage film, a second insulating film, a second charge storage film, a third insulating film, and a control electrode. In this non-volatile semiconductor storage device, the first and second charge storage films comprise a metallic material, a semi-metallic material or a semiconductor material. One of the first, second, and third insulating films is a multi-layered insulating film formed by layering multiple insulating films. This non-volatile semiconductor storage device further has a film comprising of any one of an oxide film, nitride film, boride film, sulfide film, and carbide film that is in contact with one interface of the laminated insulating film and contains one type of atom selected from aluminum, boron, alkaline earth metal, and transition metal at a concentration in the range of 1E12 atoms/cm 2 to 1E16 atoms/cm 2 .

Claims (17)

1. An integrated circuit memory, comprising:

a semiconductor layer;

a first charge storage layer overlying the semiconductor layer;

a first dielectric overlying the first charge storage layer;

a first metal layer overlying the first dielectric;

a second dielectric overlying the first metal layer;

a second charge storage layer overlying the second dielectric; and

a gate electrode overlying the second charge storage layer, wherein the first and second dielectric comprise an oxide, a nitride, or combinations of an oxide and a nitride.

2. The integrated circuit memory of claim 1 , further including a tunnel insulating layer contacting the first charge storage layer.

3. The integrated circuit memory of claim 2 , wherein the tunnel insulating layer includes a third dielectric layer overlying the semiconductor layer;

a second metal layer overlying the third dielectric layer; and

a fourth dielectric overlying the second metal layer.

4. The integrated circuit memory of claim 1 , wherein the metal layer includes any one type of atomic species selected from aluminum, a transition metal, alkaline earth metals, boron and sulpher.

5. The integrated circuit memory of claim 1 , wherein the first metal layer comprises aluminum oxide.

6. The integrated circuit of claim 5 , wherein the aluminum layer comprises at least 1E12 atoms/cm 2 .

7. The integrated circuit of claim 5 , wherein the aluminum layer comprises less than 1E16 atoms/cm 2 .

8. The integrated circuit memory of claim 1 , further including an interpoly dielectric film overlaying the second charge storage layer and provided below the gate electrode, the interpoly dielectric film having at least two dielectric layers with a metal layer interposed therebetween.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2013
From: TANAKA, MASAYUKI; TORATANI, KENICHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 030750/0270 →
Priority Claims (1)
JP 2012-195224 · Sep 5, 2012 · national
Continuity (1)
Related Publication 20140061756A1 · Mar 6, 2014