Extracting clock information from a serial communications bus for use in RF communications circuitry
View Patent ↗The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.
1. Circuitry comprising:
a first radio frequency front-end (RFFE) circuit coupled to an RFFE serial communications bus and adapted to during a non-communications operating mode:
extract clock information from the RFFE serial communications bus; and
generate a first clock signal based on the clock information; and
at least a second RFFE circuit, such that each of the at least the second RFFE circuit is coupled to the RFFE serial communications bus, and during a communications operating mode, at least the second RFFE circuit is adapted to react to at least one of a plurality of commands from the RFFE serial communications bus.
2. The circuitry of claim 1 wherein the RFFE serial communications bus is adapted to provide and the first RFFE circuit is adapted to receive a first enable signal, which:
during the communications operating mode, is in an asserted state; and
during the non-communications operating mode, is in a de-asserted state.
3. The circuitry of claim 1 wherein the RFFE serial communications bus is adapted to provide an RFFE clock signal and an RFFE data signal.
4. The circuitry of claim 3 wherein during the non-communications operating mode:
the RFFE clock signal is adapted to provide the clock information; and
the RFFE data signal is in a de-asserted state.
5. The circuitry of claim 3 wherein during the non-communications operating mode, the RFFE data signal is adapted to provide the clock information.
6. The circuitry of claim 3 wherein during the non-communications operating mode:
the RFFE clock signal is adapted to provide the clock information; and
a second clock signal is based on the RFFE data signal.
7. The circuitry of claim 3 wherein:
during the non-communications operating mode, the RFFE clock signal is adapted to provide the clock information and while providing the clock information, the RFFE clock signal has a first frequency; and
during the communications operating mode, the RFFE clock signal has a second frequency, which is not equal to the first frequency.
8. The circuitry of claim 1 wherein the first RFFE circuit comprises a direct current (DC)-to-DC converter adapted to:
receive the first clock signal, such that a switching frequency of the DC-to-DC converter is based on a frequency of the first clock signal; and
provide a power output signal from the DC-to-DC converter.
9. The circuitry of claim 8 further comprising a radio frequency (RF) power amplifier (PA), which is adapted to receive and amplify an RF signal based on a PA envelope power signal to provide an RF output signal and the power output signal is the PA envelope power signal.
10. The circuitry of claim 8 wherein the power output signal is a power supply signal.
11. The circuitry of claim 8 further comprising an RF receiver, which is adapted to receive an RF input signal having a receive frequency and the frequency of the first clock signal is selected to avoid de-sensing of the RF receiver at the receive frequency.
12. The circuitry of claim 8 wherein:
the DC-to-DC converter comprises a frequency locked loop (FLL) adapted to operate in one of a closed-loop mode and an open-loop mode;
the first RFFE circuit is further adapted to select between the closed-loop mode and the open-loop mode;
during the closed-loop mode, the switching frequency of the DC-to-DC converter is based on a present frequency of the first clock signal; and
during the open-loop mode, the switching frequency of the DC-to-DC converter is based on a previous frequency of the first clock signal, wherein the previous frequency of the first clock signal is a frequency of the first clock signal during the closed-loop mode.
13. The circuitry of claim 12 wherein the first RFFE circuit:
during the non-communications operating mode, is further adapted to generate a second clock signal based on the clock information; and
further comprises:
a temperature sensor adapted to monitor a temperature of the DC-to-DC converter, such that selection of the one of the closed-loop mode and the open-loop mode is based on temperature drift of the DC-to-DC converter; and
an analog-to-digital converter (ADC) adapted to receive and convert a temperature signal from the temperature sensor into a digital temperature signal using the second clock signal.
14. The circuitry of claim 1 wherein the first RFFE circuit comprises a digital-to-analog converter (DAC) adapted to receive and convert a digital input signal to an analog output signal using the first clock signal.
15. The circuitry of claim 14 further comprising a radio frequency (RF) power amplifier (PA), which is adapted to receive and amplify an RF signal based on a PA bias signal to provide an RF output signal, and the analog output signal is the PA bias signal.
16. The circuitry of claim 1 wherein a control system is adapted to provide the clock information on the RFFE serial communications bus.
17. The circuitry of claim 16 wherein the control system comprises a master device coupled to the RFFE serial communications bus and each of the first RFFE circuit and the at least the second RFFE circuit is a slave device.
18. The circuitry of claim 16 wherein a radio frequency integrated circuit (RFIC) provides the control system.
19. The circuitry of claim 16 further comprising the control system.
20. The circuitry of claim 16 wherein the control system is further adapted to select between the communications operating mode and the non-communications operating mode.
21. The circuitry of claim 16 wherein the control system is further adapted to during the communications operating mode, provide the plurality of commands on the RFFE serial communications bus.
22. A method comprising:
providing a first radio frequency front-end (RFFE) circuit coupled to an RFFE serial communications bus;
during a non-communications operating mode:
extracting clock information from the RFFE serial communications bus; and
generating a first clock signal based on the clock information; and
providing at least a second RFFE circuit, such that each of the at least the second RFFE circuit is coupled to the RFFE serial communications bus, and during a communications operating mode, at least the second RFFE circuit is adapted to react to at least one of a plurality of commands.