Memory controller and information processing apparatus

1. A memory controller comprising:

a first terminal connected to a Dual Inline Memory Module (DIMM) and configured to output an address signal to the DIMM;

a second terminal connected to the DIMM;

a first transmission line connected to the second terminal and configured to transmit first data to be written to the DIMM;

a second transmission line connected to the second terminal and configured to transmit second data read from the DIMM;

a determination part configured to determine a type of the DIMM having a specific address line topology, the determination being made based on Serial Presence Detection (SPD) of the DIMM;

a slew rate setting part configured to set a slew rate of the address signal based on the type of the DIMM determined by the determination part, the slew rate setting part setting a first slew rate of the address signal input to a Registered Dual Inline Memory Module (RDIMM) lower than a second slew rate of the address signal input to an Unbuffered Dual Inline Memory Module (UDIMM) in a case where the type of the DIMM determined by the determination part is an RDIMM, the slew rate setting part setting the second slew rate of the address signal in a case where the type of the DIMM determined by the determination part is a UDIMM;

a delay command generating part configured to generate a delay command for setting a delay time based on the type of the DIMM determined by the determination part;

a first delay control part inserted in series into the first transmission line and configured to control the delay time in response to the delay command generated by the delay command generating part and to delay the first data by the delay time when writing the first data in a case where the type of the DIMM determined by the determination part is an RDIMM; and

a second delay control part inserted in series into the second transmission line and configured to control the delay time in response to the delay command generated by the delay command generating part and to delay the second data by the delay time when reading the second data in a case where the type of the DIMM determined by the determination part is a UDIMM.

2. The memory controller as claimed in claim 1 , wherein the slew rate setting part includes

a slew rate set command generating part configured to generate a slew rate set command for setting the slew rate of the address signal based on the type of the DIMM determined by the determination part, and

a slew rate change part configured to change the slew rate of the address signal based on the slew rate set command generated by the slew rate set command generating part, the slew rate change part being inserted in series into an address line transmitting the address signal.

3. The memory controller as claimed in claim 2 , wherein the slew rate change part includes

a bias circuit part configured to output a current in response to the slew rate set command,

a Complementary Metal Oxide Semiconductor (CMOS) inverter circuit part configured to output the address signal having the changed slew rate in response to the output current of the bias circuit part, the CMOS inverter circuit part being driven with the address signal and being supplied with the output current of the bias circuit part.

4. The memory controller as claimed in claim 1 ,

wherein the first transmission line includes a branched section constituted of a first path and a second path connected in parallel with each other,

wherein the first delay control part includes

a first delay part inserted in series into the first path, and

a first multiplexer configured to select either of data via the first path or data via the second path in response to the delay command,

wherein the first delay control part controls the delay time by selecting one of the data via the first path and the data via the second path with the first multiplexer, and

wherein the second transmission line includes a branched section constituted of a third path and a fourth path connected in parallel with each other,

wherein the second delay control part includes

a second delay part inserted in series into the third path, and

a second multiplexer configured to select either of data via the third path or data via the fourth path in response to the delay command,

wherein the second delay control part controls the delay time by selecting one of the data via the third path and the data via the fourth path with the second multiplexer.

5. The memory controller as claimed in claim 4 , wherein the second delay control part selects the data via the third path when reading the second data from the UDIMM, and selects data via the fourth path when writing the first data to the UDIMM, and

wherein the first delay control part selects the data via the first path when reading the second data from the RDIMM, and selects data via the second path when writing the first data to the RDIMM.

6. An information processing apparatus comprising:

a processor;

a memory device; and

the memory controller as claimed in claim 1 configured to transmit data between the processor and the memory device.

7. The memory controller as claimed in claim 1 , wherein the delay command generating part generates the delay command for setting the delay time to one cycle time of a system clock when writing the data in a case where the type of the DIMM determined by the determination part is the RDIMM.

8. The memory controller as claimed in claim 1 , wherein the delay command generating part generates the delay command for setting the delay time to one cycle time of a system clock when reading the data in a case where the type of the DIMM determined by the determination part is the UDIMM.