Ground-referenced single-ended system-on-package

1. A system, comprising:

a first processor chip configured to include a first ground-referenced single-ended signaling (GRS) interface circuit comprising:

a first GRS driver circuit, configured to:

pre-charge a first capacitor to store a first charge during a first pre-charge phase; and

drive an output signal relative to a ground network based on the first charge during a first drive phase;

a system function chip configured to include a second GRS interface circuit, comprising a second GRS driver circuit configured to:

pre-charge a second capacitor to store a second charge during a second pre-charge phase, wherein the second pre-charge phase overlaps in time with the first drive phase; and

drive the output signal relative to a ground network based on the second charge during a second drive phase, wherein the first pre-charge phase overlaps in time with the second drive phase; and

a multi-chip module (MCM) package configured to include the first processor chip and the system function chip; and

a first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the second GRS interface circuit.

2. The system of claim 1 , wherein the first GRS interface circuit comprises

a receiver circuit, configured translate a ground-referenced single-ended input signal to a corresponding logic signal,

wherein the first set of electrical traces comprise the input signal, the output signal, and the ground network.

3. The system of claim 1 , further comprising:

a first memory subsystem included within the MCM package and configured to include a third GRS interface circuit;

a fourth GRS interface circuit included within the first processor chip; and

a second set of electrical traces fabricated within the MCM package and configured to couple the third GRS interface circuit to the fourth GRS interface circuit.

4. The system of claim 3 , wherein the first memory subsystem comprises at least two stacked chips.

5. The system of claim 1 , further comprising:

a second processor chip included within the MCM package and configured to include a third GRS interface circuit;

a fourth GRS interface circuit included within the first processor chip; and

a second set of electrical traces fabricated within the MCM package and configured to couple the third GRS interface circuit to the fourth GRS interface circuit.

6. The system of claim 5 , further comprising:

a first memory subsystem included within the MCM package and configured to include a fifth GRS interface circuit;

a sixth GRS interface circuit included within the second processor chip; and

a third set of electrical traces fabricated within the MCM package and configured to couple the fifth GRS interface circuit to the sixth GRS interface circuit.

7. The system of claim 1 , further comprising:

a second processor chip included within the MCM package and configured to include a third GRS interface circuit;

a fourth GRS interface circuit included within the system function chip; and

a second set of electrical traces fabricated within the MCM package and configured to couple the third GRS interface circuit to the fourth GRS interface circuit,

wherein the system function chip is configured to forward data between the first processor chip and the second processor chip.

8. The system of claim 7 , further comprising:

a first memory subsystem included within the MCM package and configured to include an fifth GRS interface circuit;

a sixth GRS interface circuit included within the system function chip; and

a third set of electrical traces fabricated within the MCM package and configured to couple the fifth GRS interface circuit and the sixth GRS interface circuit,

wherein the system function chip is configured to forward data between the first memory subsystem and at least the first processor chip or the second processor chip.

9. The system of claim 5 , further comprising:

a fifth GRS interface circuit included within the second processor chip;

a sixth GRS interface circuit included within the system function chip; and

a third set of electrical traces fabricated within the MCM package and configured to couple the fifth GRS interface circuit to the sixth GRS interface circuit,

wherein the first processor chip is configured to communicate directly with the second processor chip and with the system function chip, the second processor chip is configured to communicate directly with the first processor chip and with the system function chip, and the system function chip is configured to communicate directly with the first processor chip and with the second processor chip.

10. The system of claim 5 , wherein the first processor chip and the second processor chip are manufactured using different fabrication processes.

11. The system of claim 1 , wherein the system function chip comprises a coder-decoder (CODEC) circuit.

12. The system of claim 1 , wherein the system function chip comprises a signal processor circuit.

13. The system of claim 1 , further comprising a modem chip included within the MCM package and configured to communicate with the first processor chip.

14. The system of claim 13 , wherein the modem chip communicates with the first processor chip through the system function chip.

15. The system of claim 13 , wherein the modem chip implements a wireless local area network modem.

16. The system of claim 13 , wherein the first processor chip and the modem chip are manufactured using different fabrication processes.

17. The system of claim 1 , further comprising an interface unit chip included within the MCM package and configured to communicate with the first processor chip.

18. The system of claim 1 , wherein the MCM package includes an organic substrate or a silicon substrate.

19. A non-transitory computer readable medium, comprising:

code representing a first set of electrical traces configured to couple a first ground-referenced single-ended signaling (GRS) interface circuit of a first processor chip to a second GRS interface circuit of a system function chip within a multi-chip module (MCM) package, the first GRS interface circuit comprising:

a first GRS driver circuit, configured to:

pre-charge a first capacitor to store a first charge during a first pre-charge phase; and

drive an output signal relative to a ground network based on the first charge during a first drive phase; and

the second GRS interface circuit comprising:

a second GRS driver circuit, configured to:

pre-charge a second capacitor to store a second charge during a second pre-charge phase wherein the second pre-charge phase overlaps in time with the first drive phase; and

drive the output signal relative to a ground network based on the second charge during a second drive phase, wherein the first pre-charge phase overlaps in time with the second drive phase; and

code representing a second set of electrical traces configured to couple the first processor chip to a second processor chip within the MCM package;

code representing a third set of electrical traces configured to couple the first processor chip to a first memory subsystem within the MCM package; and

code representing a fourth set of electrical traces configured to couple the second processor chip to a second memory subsystem within the MCM package,

wherein the first set of electrical traces, the second set of electrical traces, the third set of electrical traces, and the fourth set of electrical traces comprise ground-referenced single-ended signal lines.

20. The non-transitory computer readable medium of claim 19 , further comprising:

code representing a fifth set of electrical traces configured to couple the system function chip to a modem chip within the MCM package.

21. A method for transmitting data within a multi-chip module (MCM) package, comprising:

generating an access request within an initiator chip within the MCM package for transmission to a target chip within the MCM package;

serializing the access request to generate a plurality of individual bits comprising the access request;

pre-charging a first capacitor based on a first bit comprising the plurality of individual bits during a first pre-charge phase;

pre-charging a second capacitor based on a second bit comprising the plurality of individual bits during a second pre-charge phase;

transmitting a first data bit based on a charge associated with the first capacitor during a first drive phase, wherein the second pre-charge phase overlaps in time with the first drive phase;

transmitting a second data bit based on a charge associated with the second capacitor during a second drive phase, wherein the first pre-charge phase overlaps in time with the second drive phase;

receiving the first data bit within the target chip; and

receiving the second data bit within the target chip,

wherein the first data bit and the second data bit are transmitted from the initiator chip to the target chip through a set of electrical traces fabricated within the MCM package.

22. The method of claim 21 , further comprising:

determining which device is a destination device for the access request based on an address field associated with the access request; and

forwarding the access request to the destination device.