Parallel FET solid state relay utilizing commutation FETs
View Patent ↗A solid state relay circuit is disclosed, containing a first and second group of FETs, the groups being connected in parallel. The first FET group contains commutation FETs capable of handling the commutation load of the circuit. The second FET group contains secondary FETs of lower resistance than the commutation FETs. The circuit is configured such that, when the circuit is activated, the commutation FETs are driven on before the secondary FETs. The circuit is also configured such that, when the circuit is deactivated, the commutation FETs are driven off only after the secondary FETs.
1. A solid state relay circuit, comprising:
a first FET group containing at least one commutation FET;
a second FET group containing at least one secondary FET;
said first and second FET groups being connected in parallel;
said secondary FETs each having a lower resistance than each of said commutation FETs;
said circuit configured such that when said circuit is activated said commutation FETs of said first FET group are driven on before said secondary FETs of said second FET group; and
said circuit further configured such that when said circuit is deactivated said commutation FETs of said first FET group are driven off after said secondary FETs of said second FET group.
2. The circuit of claim 1 wherein said commutation FETs of said first FET group are each effective to tolerate the electrical stress caused by the activation and deactivation of said circuit.
3. The circuit of claim 1 wherein said commutation FETs of said first FET group are each effective to commute a maximum possible fault current of said circuit.
4. The circuit of claim 1 wherein said circuit is configured such that the delay of a gate drive causes said commutation FETs of said first FET group to be driven on before said secondary FETs of said second FET group when said circuit is activated and causes said commutation FETs of said first FET group to be driven off after said secondary FETs of said second FET group when said circuit is deactivated.
5. A solid state relay circuit, comprising
at least one commutation FET connected in parallel to at least one secondary FET;
a first delay device connected in series at a first end to a source of drive power and at a second end in series to said commutation FETs;
a second delay device connected at a first end in series to a source of drive power and at a second end in series to said secondary FETs;
said first and second delay devices effective in conjunction to cause said commutation FETs to be driven on before said secondary FETs when said circuit is activated and to cause said commutation FETs to be driven off after said secondary FETs when said circuit is deactivated.
6. The circuit of claim 5 wherein said first and second delay devices each comprise a resistor and a diode.
7. The circuit of claim 6 wherein said commutation FETs are each effective to tolerate the electrical stress caused by the activation and deactivation of said circuit.
8. The circuit of claim 5 wherein said commutation FETs are each effective to commute a maximum possible fault current of said circuit.