Synthetic processing diversity with multiple architectures within a homogeneous processing environment
View Patent ↗A method of increasing processing diversity on a computer system includes: loading a plurality of instruction streams, each of the plurality of instruction streams being equivalent; executing, in a context, a first stream of the plurality of instruction streams; stopping execution of the first stream at a first location of the first stream; and executing, in the context, a second stream of the plurality of instruction streams at a second location of the second stream, the second location corresponding to the first location of the first stream.
1. A method of increasing processing diversity on a computer system, the method comprising:
a) duplicating, in a context, a computer program execution instruction stream into a plurality of instruction streams, each of the plurality of instruction streams being equivalent;
b) encoding each of the plurality of instruction streams using a different encoding key;
c) decoding a first instruction stream of the plurality of instruction streams;
d) executing said decoded first instruction stream of the plurality of instruction streams to execute a first portion of the computer program;
e) stopping execution of the first decoded instruction stream at a first location of the first instruction stream;
f) decoding a second instruction stream of the plurality of instruction streams starting at a second location of the second instruction stream, the second location corresponding to the first location of the first instruction stream; and
g) executing said decoded second instruction stream of the plurality of instruction streams at said second location of the second instruction stream to execute a second portion of the computer program immediately following the first portion, wherein steps c to g are repeated until all of the plurality of instruction streams are decoded and executed, and
wherein the first location of the first instruction stream and the second location of the second instruction stream are randomly selected.
2. The method of claim 1 , wherein each of the plurality of instruction streams is loaded from a binary and is identical to the rest of the plurality of instruction streams.
3. The method of claim 1 , wherein each of the plurality of instruction streams is generated from an instruction stream loaded from a binary and is identical to the rest of the plurality of instruction streams.
4. The method of claim 1 , wherein the method of increasing processing diversity on the computer system is performed using a virtualization program executing on the computer system.
5. The method of claim 1 , wherein the method of increasing processing diversity on the computer system is performed using a hardware instruction selector.
6. A non-transitory computer readable medium embodying program instructions for execution by a data processing apparatus, the program instructions adapting the processing apparatus for:
a) duplicating, in a context, a computer program execution instruction stream into a plurality of instruction streams, each of the plurality of instruction streams being equivalent;
b) encoding each of the plurality of instruction streams using a different encoding key;
c) decoding a first instruction stream of the plurality of instruction streams;
d) executing said decoded first instruction stream of the plurality of instruction streams to execute a first portion of the computer program;
e) stopping execution of the first decoded instruction stream at a first location of the first instruction stream;
f) decoding a second instruction stream of the plurality of instruction streams starting at a second location of the second instruction stream, the second location corresponding to the first location of the first instruction stream; and
g) executing said decoded second instruction stream of the plurality of instruction streams at said second location of the second instruction stream to execute a second portion of the computer program immediately following the first portion, wherein steps c to g are repeated until all of the plurality of instruction streams are decoded and executed, and
wherein the first location of the first instruction stream and the second location of the second instruction stream are randomly selected.
7. The non-transitory computer readable medium of claim 6 , wherein each of the plurality of instruction streams is loaded from a binary and is identical to the rest of the plurality of instruction streams.
8. The non-transitory computer readable medium of claim 6 , wherein each of the plurality of instruction streams is generated from an instruction stream loaded from a binary and is identical to the rest of the plurality of instruction streams.
9. The non-transitory computer readable medium of claim 6 , wherein the non-transitory computer readable medium further embodies a virtualization program, and
wherein the virtualization program comprises the program instructions.
10. A computer system comprising a processor and memory storing program instructions, the computer system being configured to:
a) duplicating, in a context, a computer program execution instruction stream into a plurality of instruction streams, each of the plurality of instruction streams being equivalent;
b) encode each of the plurality of instruction streams using a different encoding key;
c) decode a first instruction stream of the plurality of instruction streams;
d) execute said decoded first instruction stream of the plurality of instruction streams to execute a first portion of the computer program;
e) stop execution of the first decoded instruction stream at a first location of the first instruction stream;
f) decode a second instruction stream of the plurality of instruction streams starting at a second location of the second instruction stream, the second location corresponding to the first location of the first instruction stream; and
g) execute said decoded second instruction stream of the plurality of instruction streams at said second location of the second instruction stream to execute a second portion of the computer program immediately following the first portion, wherein steps c to g are repeated until all of the plurality of instruction streams are decoded and executed, and
wherein the first location of the first instruction stream and the second location of the second instruction stream are randomly selected.
11. The system of claim 10 , wherein each of the plurality of instruction streams is loaded from a binary and is identical to the rest of the plurality of instruction streams.
12. The system of claim 10 , wherein each of the plurality of instruction streams is generated from an instruction stream loaded from a binary and is identical to the rest of the plurality of instruction streams.
13. The system of claim 10 , wherein a virtualization program executing on the computer system configures the computer system to: execute, in the context, the first stream of the plurality of instruction streams; stop execution of the first stream at the first location of the first stream; and execute, in the context, the second stream of the plurality of instruction streams.
14. The system of claim 10 , further comprising a hardware instruction selector configured to execute, in the context, the first stream of the plurality of instruction streams; stop execution of the first stream at the first location of the first stream; and execute, in the context, the second stream of the plurality of instruction streams.