IP Library Granted Patent US 9,294,117
Granted Patent B2
US 9,294,117 · App. 13/939,595 · Granted Mar 22, 2016

Method and system for gain control for time-interleaved analog-to-digital convertor (ADC)

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Quick Facts
Patent No.
US 9,294,117
App. No.
13/939,595
Granted
Mar 22, 2016
Kind
B2
Abstract

A system for processing signals may be configured to apply digital conversion to analog signals, and to apply, prior to the analog-to-digital conversion, a gain to at least a portion of the analog signals. The gain may be controlled and/or adjusted based on processing of digital output generated based on the analog-to-digital conversion. The system may comprise a plurality of sampling slices, which may be configured to provide the analog-to-digital conversion in interleaved (e.g., time-interleaved) manner. Each of the sampling slices may comprise a dedicated gain element, for applying gain to signals handled by the corresponding slice. The gain applied by the gain elements of the sampling slices may be controlled, independently, collectively, and/or in based on grouping into subsets. The gain may be controlled based on application of a particular gain control algorithm, which may be selected from a plurality of predefined algorithms.

Claims (40)

1. A method, comprising:

in an electronic system:

processing an analog signal, wherein the processing comprises:

performing analog-to-digital conversion of the analog signal; and

applying, prior to the analog-to-digital conversion, gain to at least a portion of the analog signal; and

controlling the gain based on processing of a digital output generated based on the analog-to-digital conversion.

2. The method of claim 1 , comprising configuring the analog-to-digital conversion to function in an interleaved manner.

3. The method of claim 1 , comprising applying the analog-to-digital conversion via a plurality of slices, configured such that the combined operation of the plurality of slices provides overall analog-to-digital conversion of the analog signal.

4. The method of claim 3 , comprising applying separate gain in each of the plurality of the slices.

5. The method of claim 4 , comprising controlling the application of the separate gain in each of the plurality of the slices independently, collectively, and/or in based on grouping into subsets.

6. The method of claim 1 , comprising controlling the gain based on a particular gain control algorithm, selected from a plurality of predefined control algorithms.

7. The method of claim 6 , wherein the plurality of predefined control algorithms comprises:

a first algorithm by which remaining slices in a multi-slice analog-to-digital convertor (ADC) based implementation are adjusted based on adjustment to one slice and/or error detected corresponding to conversion or sampling performed via the one slice;

a second algorithm by which slices in a multi-slice analog-to-digial convertor (ADC) based implementation are adjusted in predictive manner based on analysis of the sloping of the resultant signals corresponding to at least one of the slices, when sloping is indicative of occurrence of clipping; and

a third algorithm configured such that at least some of gains corresponding to some of slices in a multi-slice analog-to-digital convertor (ADC) based implementation are adjusted in a predetermined and/or a random manner to ensure that occurrence of clipping is prevented.

8. A system, comprising:

one or more circuits for use in a signal processing component, the signal processing component being configured to perform a plurality of processing operations, comprising analog-to-digital conversion, the one or more circuits being operable to:

apply analog-to-digital conversion to a received analog signal;

apply, prior to the analog-to-digital conversion, gain to at least a portion of the analog signal; and

control the gain based on processing of a digital output generated based on the analog-to-digital conversion.

9. The system of claim 8 , wherein the analog-to-digital conversion is configured to function in an interleaved manner.

10. The system of claim 8 , wherein the one or more circuits are operable to apply the analog-to-digital conversion via a plurality of slices, such that the combined operation of the plurality of slices provides overall analog-to-digital conversion of the analog signal.

11. The system of claim 10 , wherein the one or more circuits are operable to apply separate gain in each of the plurality of the slices.

12. The system of claim 11 , wherein the one or more circuits are operable to control the application of the separate gain in each of the plurality of the slices independently, collectively, and/or in based on grouping into subsets.

13. The system of claim 8 , wherein the one or more circuits are operable to control the gain based on a particular gain control algorithm, selected from a plurality of predefined control algorithms.

14. The system of claim 13 , wherein the plurality of predefined control algorithms comprises:

a first algorithm by which remaining slices in a multi-slice analog-to-digital convertor (ADC) based implementation are adjusted based on adjustment to one slice and/or error detected corresponding to conversion or sampling performed via the one slice;

a second algorithm by which slices in a multi-slice analog-to-digital convertor (ADC) based implementation are adjusted in predictive manner based on analysis of the sloping of the resultant signals corresponding to at least one of the slices, when sloping is indicative of occurrence of clipping; and

a third algorithm configured such that at least some of gains corresponding to some of slices in a multi-slice analog-to-digital convertor (ADC) based implementation are adjusted in predetermined and/or random manner to ensure that occurrence of clipping is prevented.

15. A system, comprising:

a signal processing component that is configured to perform a plurality of processing operations, the signal processing component comprising:

a plurality of sampling slices, for use in generating a digital output based on an analog signal, wherein each sampling slice comprises:

an analog-to-digital converter (ADC) element, for applying analog-to-digital conversion to at least a portion of the received analog signal; and

a gain element, for applying within a corresponding sampling slice and prior to application of analog-to-digital conversion via the ADC element, gain to at least the portion of the analog signal; and

a processing circuit for processing the digital output, wherein the processing circuit is operable to generate gain related information, for use in controlling gain applied via gain elements corresponding to the plurality of sampling slices.

16. The system of claim 15 , wherein the signal processing component comprises a buffering circuit, for buffering the analog signal before inputting the plurality of slices.

17. The system of claim 15 , wherein the plurality of sampling slices is configured to perform overall analog-to-digital conversion of the analog signal in time-interleaved manner.

18. The system of claim 15 , wherein the signal processing component is incorporated into a receiving device, with the analog signal being received from a corresponding transmitting device.

19. The system of claim 18 , wherein the receiving device is operable to setup with the corresponding transmitting device, one or more sideband channels for exchanging control related data.

20. The system of claim 19 , wherein the receiving device is operable to receive from the corresponding transmitting device, via the one or more sideband channels, gain control related data that is utilized by the signal processing component in controlling gain applied in the plurality of sampling slices.

Assignments (5)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2021
From: MUFG UNION BANK, N.A.
To: MAXLINEAR, INC.; EXAR CORPORATION; MAXLINEAR COMMUNICATIONS LLC
Reel/Frame 056656/0204 →
SUCCESSION OF AGENCY (REEL 042453 / FRAME 0001) Recorded Jul 1, 2020
From: JPMORGAN CHASE BANK, N.A.
To: MUFG UNION BANK, N.A.
Reel/Frame 053115/0842 →
SECURITY AGREEMENT Recorded May 12, 2017
From: MAXLINEAR, INC.; ENTROPIC COMMUNICATIONS, LLC (F/K/A ENTROPIC COMMUNICATIONS, INC.); EXAR CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042453/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 20, 2013
From: PULLELA, RAJA; LING, CURTIS
To: MAXLINEAR, INC.
Reel/Frame 031638/0248 →