TRANSISTOR WITH SELF-ALIGNED TERMINAL CONTACTS
An embodiment of a MOS transistor includes a layer of semiconductor material, drain regions having a first conductivity type alternately formed in the layer with body regions having a second conductivity type, a first insulating layer disposed over the surface of the layer of semiconductor material, at least one gate-precursor region of conductive material disposed over the first insulating layer, a second insulating layer disposed over the first insulating layer and the gate-precursor region, a third insulating layer disposed over the second insulating layer, at least one source opening formed by removing overlapping portions of the second insulating layer, the third insulating layer, the gate-precursor region, and by at least partially removing a corresponding portion of the first insulating layer. The embodiment may also include at least one source-precursor region extending into the layer of semiconductor material from a surface portion below the at least one source opening.
1 - 10 . (canceled)
11 . A transistor, comprising:
a drain region;
a body region disposed adjacent to the drain region;
a first source region disposed in the body region;
a body-contact region disposed in the body region beneath the source region; and
a source-body contact having a side in contact with the source region and having a bottom in contact with the body-contact region.
12 . The transistor of claim 11 wherein the body region is disposed in the drain region.
13 . The transistor of claim 11 wherein:
the drain and source regions are of a first conductivity type; and
the body and body-contact regions are of a second conductivity type.
14 . The transistor of claim 11 , further comprising:
an opening that extends through the source region and into the body-contact region; and
the body contact is disposed in the opening.
15 . The transistor of claim 11 , further comprising:
a second source region disposed in the body region over the body-contact region; and
wherein the source-body contact is disposed between the first and second source regions and has a side in contact with the second source region.
16 . The transistor of claim 15 wherein the source-body contact has a same side in contact with the first and second source regions.
17 . The transistor of claim 15 wherein the source-body contact has respective sides in contact with the first and second source regions.
18 . The transistor of claim 11 wherein the body contact region is in contact with a side of the source-body contact.
19 . The transistor of claim 11 , further comprising:
a gate insulator disposed over a portion of the body region disposed between the drain region and the source region; and
a gate disposed over the gate insulator.
20 . An integrated circuit, comprising:
a layer of semiconductor material;
a drain region disposed in the layer;
a body region disposed in the layer adjacent to the drain region;
a source region disposed in the body region;
a body-contact region disposed in the body region beneath the source region; and
a source-body contact having a side in contact with the source region and having a bottom in contact with the body-contact region.
21 . The integrated circuit of claim 20 , further comprising:
a gate insulator disposed over a portion of the layer disposed between the drain region and the source region; and
a gate disposed over the gate insulator.
22 . A system, comprising;
a first integrated circuit, including
a layer of semiconductor material,
a drain region disposed in the layer,
a body region disposed in the layer adjacent to the drain region,
a source region disposed in the body region,
a body-contact region disposed in the body region beneath the source region, and
a source-body contact having a side in contact with the source region and having a bottom in contact with the body-contact region; and
a second integrated circuit coupled to the first integrated circuit.
23 . The system of claim 22 wherein the first and second integrated circuits are disposed on a same die.
24 . The system of claim 22 wherein the first and second integrated circuits are disposed on respective dies.
25 . The system of claim 22 wherein at least one of the first and second integrated circuits includes a computing circuit.
26 . A method, comprising:
forming through a first opening above a body region a source region in the body region;
forming through the first opening a second opening in the body region adjacent to the source region;
forming through the second opening a body-contact region in the body region; and
forming a source-body contact in the second opening.
27 . The method of claim 26 , further comprising forming the first opening in a layer that is disposed above the body region;
28 . The method of claim 26 wherein forming the second opening includes forming the second opening through the source region.
29 . The method of claim 26 wherein forming the second opening includes dividing the source region into first and second separate source regions with the second opening.
30 . The method of claim 26 wherein forming the second opening includes:
forming a layer over a side and a bottom of the first opening to form an intermediate opening; and
forming the second opening by removing through the intermediate opening a portion of the layer disposed over the bottom of the first opening.