IP Library Granted Patent US 9,639,214
Granted Patent B2
US 9,639,214 · App. 13/947,617 · Granted May 2, 2017

Utilizing chip-on-glass technology to jumper routing traces

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Quick Facts
Patent No.
US 9,639,214
App. No.
13/947,617
Granted
May 2, 2017
Kind
B2
Abstract

A chip-on-glass device comprises a chip-on-glass substrate, a metal layer, and a plurality of chip-on-glass connection bumps. The metal layer comprises a plurality of passive jumper routing traces. The plurality of chip-on-glass connection humps is coupled with passive jumper routing traces of the plurality of passive jumper routing traces.

Claims (31)

1. A single-layer capacitive sensor comprising:

a sensor substrate;

a plurality of receiver electrodes disposed in a first layer above said sensor substrate;

a plurality of transmitter electrodes disposed in said first layer above said sensor substrate;

a plurality of routing traces disposed in said first layer above said sensor substrate, wherein at least a first one of said plurality of routing traces is coupled to a receiver electrode of said plurality of receiver electrodes and a different and second one of said plurality of routing traces is coupled to one of said plurality of transmitter electrodes;

a chip-on-glass device, wherein no active components are disposed within said chip-on-glass device, said chip-on-glass device comprising:

a chip-on-glass substrate which is a separate entity from said sensor substrate;

a metal layer comprising a plurality of passive jumper routing traces; and

a plurality of chip-on-glass connection bumps coupled with passive jumper routing traces of said plurality of passive jumper routing traces; and

at least one electrical connection between a chip-on-glass connection bump of said plurality of chip-on-glass connection bumps and a transmitter electrode of said plurality of transmitter electrodes or a receiver electrode of said plurality of receiver electrodes.

2. The single-layer capacitive sensor of claim 1 , further comprising:

a plurality of receiver electrode traces disposed on said sensor substrate.

3. The single-layer capacitive sensor of claim 2 , wherein at least some said plurality of receiver electrode traces pass beneath said chip-on-glass substrate.

4. The single-layer capacitive sensor of claim 1 , wherein said metal layer is the only metal layer of said chip-on-glass device.

5. The single-layer capacitive sensor of claim 1 , wherein said metal layer is configured to passively multiplex a single routing trace into a plurality of routing traces.

6. An input device comprising:

a single-layer capacitive sensor comprising:

a sensor substrate;

a plurality of receiver electrodes disposed in a first layer above said sensor substrate; and

a plurality of transmitter electrodes disposed in said first layer above said sensor substrate;

a plurality of routing traces disposed in said first layer above said sensor substrate, wherein at least a first one of said plurality of routing traces is coupled to a receiver electrode of said plurality of receiver electrodes and a different and second one of said plurality of routing traces is coupled to one of said plurality of transmitter electrodes;

a chip-on-glass device, wherein no active components are disposed within said chip-on-glass device, said chip-on-glass device comprising:

a chip-on-glass substrate which is a separate entity from said sensor substrate;

a metal layer comprising a plurality of passive jumper routing traces; and

a plurality of chip-on-glass connection bumps coupled with passive jumper routing traces of said plurality of passive jumper routing traces; and

at least one electrical connection between a chip-on-glass connection bump of said plurality of chip-on-glass connection bumps and a transmitter electrode of said plurality of transmitter electrodes or a receiver electrode of said plurality of receiver electrodes.

7. The input device of claim 6 , further comprising:

a plurality of receiver electrode traces disposed on said sensor substrate.

8. The input device of claim 7 , wherein at least some said plurality of receiver electrode traces pass beneath said chip-on-glass substrate.

9. The input device of claim 6 , wherein said metal layer is one of a plurality of metal layers of said chip-on-glass device.

10. The input device of claim 6 , wherein said metal layer is configured to passively multiplex a single trace into a plurality of routing traces.

Assignments (3)
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
SECURITY INTEREST Recorded Oct 3, 2014
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 033889/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2013
From: DUNPHY, JIM; REYNOLDS, JOSEPH KURTH
To: SYNAPTICS INCORPORATED
Reel/Frame 030848/0970 →