Clock domain crossing serial interface, direct latching, and response codes
View Patent ↗Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.
1. A method, comprising:
identifying a data communication command received over a serial interface;
resolving an address received over the serial interface to access a register bank;
communicating data over the serial interface;
decoding the address to obtain information associated with the address; and
based on the information associated with the address and at least some content of the data communication command, communicating a write error response code over the serial interface; and
accounting for a clock domain crossing in association with communicating the data.
2. The method of claim 1 , wherein resolving the address comprises:
decoding the address to determine whether the address falls within a direct latch address range of the register bank; and
when the address falls within the direct latch address range, directly latching the data into a direct latch register of the register bank based on a clock signal of the serial interface.
3. The method of claim 1 wherein resolving the address comprises:
decoding the address to determine whether the address falls within a direct latch address range of the register bank; and
when the address does not fall within the direct latch address range, storing the data into a first-in-first-out (FIFO) register.
4. The method of claim 3 , further comprising writing data from the FIFO register to the register bank.
5. The method of claim 1 , further comprising: when the data communication command comprises a write command, communicating the data over the serial interface for writing to the register bank; and
after a wait time, communicating a response code over the serial interface.
6. The method of claim 1 , wherein decoding the address to obtain information comprises decoding the address to determine whether the address falls within a direct latch address range of the register bank, wherein the at least some content of the data communication command comprises a write command, and wherein communicating the write error response code over the serial interface further comprises: determining whether a first-in-first-out (FIFO) register is full; and
when the FIFO register is full, communicating the write error response code.
7. The method of claim 1 , further comprising, when the data communication command comprises a read command and the address overlaps with data in a first-in-first-out (FIFO) register waiting to be written to the register bank, communicating a read error response code.
8. The method of claim 1 , further comprising generating a multiplexed output clock, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.
9. The method of claim 8 , wherein generating the multiplexed output clock comprises multiplexing between a clock of the serial interface and a system clock.
10. A system, comprising:
a communications interface configured to identify a data communication command received over a serial interface; and
a register control circuit configured to:
resolve an address received over the serial interface to access a register bank;
communicate data over the serial interface;
decode the address to obtain information associated with the address; and
account for a clock domain crossing in association with data communication over the serial interface,
wherein the communications interface is configured to communicate one of a write error response code or a read error response code, when a write or read error condition occurs.
11. The system of claim 10 , wherein the register control circuit further:
decodes the address to determine whether the address falls within a direct latch address range of the register bank; and
directly latches the data into a direct latch register of the register bank based on a clock signal of the serial interface when the address falls within the direct latch address range.
12. The system of claim 10 , wherein the register control circuit further:
decodes the address to determine whether the address falls within a direct latch address range of the register bank; and
stores the data into a first-in-first-out (FIFO) register when the address does not fall within the direct latch address range.
13. The system of claim 10 , further comprising a clock multiplexer that generates a multiplexed output clock, for writing to and reading from the register bank, based on at least one of a current system operating state and a system refresh control signal from a host processor.
14. The system of claim 13 , wherein the clock multiplexer multiplexes between a clock of the serial interface and a system clock.
15. A method, comprising:
identifying a data communication command received over a serial interface;
decoding an address to determine whether the address falls within a direct latch address range of a register bank;
when the address does not fall within the direct latch address range of the register bank, storing the data into a first-in-first-out (FIFO) register:
communicating the data over the serial interface; and
accounting for a clock domain crossing when directly latching the data into a direct latch register of the register bank based on a clock signal of the serial interface.
16. The method of claim 15 , further comprising, after a wait time, communicating a response code over the serial interface.
17. The method of claim 15 , further comprising generating a multiplexed output clock, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.
18. The method of claim 15 , wherein the address is received over the serial interface, and further comprising when the data communication command comprises a read command, communicating data over the serial interface after a wait time.
19. The method of claim 15 , further comprising when the data communication command comprises a write command and the address does not fall within the direct latch address range, determining whether a first-in-first-out (FIFO) register is full; and
when the FIFO register is full, communicating a write error response code.
20. The method of claim 15 , further comprising writing data from the FIFO register to the register bank.