Power mode register reduction and power rail bring up enhancement
Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner.
1. A method, comprising:
setting, by a power management circuit, an operating parameter for a first power rail among a plurality of power rails according to a predetermined programmed setting, wherein setting the operating parameter for the first power rail comprises writing data bits to a respective operating register including at least one power mode bit entry;
releasing a processor to start; and
receiving from the processor, via an interface of the power management circuit, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail, wherein the command to modify the operating parameter for the first power rail comprises a single command to power down power a subset of the plurality of power rails, and wherein the subset comprises at least two power rails.
2. The method of claim 1 , further comprising:
monitoring, by the power management circuit, a system parameter of a system; and
enabling the first power rail based on the system parameter.
3. The method of claim 1 , wherein the operating register for the first power rail further comprises at least one on/off bit entry.
4. The method of claim 1 , wherein the command to modify the operating parameter for the first power rail comprises a single command to modify the operating parameters for a subset of the plurality of power rails, and wherein the subset comprises at least two power rails; and
the method further comprises, according to the single command, writing data bits to a grouped operating register for the subset of power rails.
5. The method of claim 4 , wherein the grouped operating register for the subset of power rails comprises at least one power mode bit entry for each power rail in the subset of power rails.
6. The method of claim 1 , further comprising setting the operating parameter for the second power rail by writing data bits to an operating register for the second power rail.
7. The method of claim 1 , further comprising waiting a predetermined amount of time after the setting and before the releasing.
8. The method of claim 1 , further comprising communicating, via the interface of the power management circuit, system status data to the processor.
9. A power management device, comprising:
a plurality of power rails; and
a controller circuit that:
sets an operating parameter for a first power rail of the plurality of power rails according to a predetermined programmed setting by writing data bits to a respective operating register including at least one power mode bit entry;
releases a processor to start; and
in accordance with a command received from the processor, at least one of modifies the operating parameter for the first power rail or sets an operating parameter for a second power rail of the plurality of power rails, wherein the command to modify the operating parameter for the first power rail comprises a single command to power down a subset of the plurality of power rails, and wherein the subset comprises at least two power rails.
10. The device of claim 9 , wherein the controller circuit further monitors a system parameter of a system and enables the first power rail based on the system parameter.
11. The device of claim 9 , wherein the operating register of the first power rail comprises at least one on/off bit entry.
12. The device of claim 9 , further comprising:
a grouped operating register for a subset of the plurality of power rails, the subset of the plurality of power rails including the first power rail, wherein
the controller circuit further modifies the operating parameters for the subset of the plurality of power rails in accordance with a single command received from the processor by writing data bits to the grouped operating register.
13. The device of claim 12 , wherein the grouped operating register comprises at least one power mode bit entry for each power rail in the subset of the plurality of power rails.
14. The device of claim 9 , wherein the controller circuit further sets the operating parameter for the second power rail by writing data bits to an operating register for the second power rail.
15. A method, comprising:
setting, by power management circuit, an operating parameter for a first power rail among a plurality of power rails according to a predetermined programmed setting, wherein setting the operating parameter for the first power rail comprises writing data bits to a respective operating register including at least one power mode bit entry;
communicating, via an interface of the power management circuit, system status data to a processor;
receiving, via the interface of the power management circuit, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail, wherein the command to modify the operating parameter for the first power rail comprises a single command to power down a subset of the plurality of power rails, and wherein the subset comprises at least two power rails.
16. The method of claim 15 , wherein the operating register for the first power rail comprises at least one on/off bit entry.
17. The method of claim 15 , wherein the method further comprises, according to the single command, writing data bits to a grouped operating register for the subset of power rail.
18. The method of claim 15 , wherein the grouped operating register for the subset of power rails comprises at least one power mode bit entry for each power rail in the subset of power rails.
19. The method of claim 6 , wherein the operating register for the second power rail comprises at least one on/off bit entry, at least one mode bit entry, and at least one voltage bit entry.
20. The method of claim 14 , wherein the operating register for the second power rail comprises at least one on/off bit entry, at least one mode bit entry, and at least one voltage bit entry.