IP Library Granted Patent US 9,063,850
Granted Patent B2
US 9,063,850 · App. 13/951,169 · Granted Jun 23, 2015

Extended utilization area for a memory device

Inventors: Jani Hyvonen (Tampere, FI); Kimmo J. Mylly (Kirkland, FI); Jussi Hakkinen (Tampere, FI); Yevgen Gyl (Tampere, FI)
Assignee: Memory Technologies LLC
G06F12/0646G06F21/79G06F12/1441G06F12/1433G06F12/1458G06F13/1694Y02B60/1225Y02B60/1228
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Quick Facts
Patent No.
US 9,063,850
App. No.
13/951,169
Granted
Jun 23, 2015
Kind
B2
Abstract

Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Claims (74)

1. A memory device comprising:

one or more registers to store one or more predefined access profiles associated with the memory device, the one or more predefined access profiles used to determine how access to the memory device is configured for at least one usage; and

a controller configured to:

receive at least one first command to activate at least one of the one or more predefined access profiles; and

receive at least one second command to designate the at least one of the one or more predefined access profiles such that at least a portion of the memory device is configured according to the at least one of the one or more predefined access profiles for the at least one usage.

2. The memory device of claim 1 , wherein the at least one first command activates two or more of the predetermined access profiles in parallel.

3. The memory device of claim 1 , wherein at least one of the one or more predefined access profiles comprises a default access profile.

4. The memory device of claim 1 , wherein the memory device comprises an embedded MultiMedia Card (eMMC) device.

5. The memory device of claim 1 , wherein the controller is configured to conduct two or more simultaneous memory access operations.

6. The memory device of claim 5 , wherein the controller is configured to assign access priority levels to resolve conflicting simultaneous memory access operations.

7. The memory device of claim 1 , wherein the controller is configured to interleave two or more simultaneous memory access operations.

8. The memory device of claim 7 , wherein the controller is configured to assign access priority levels to resolve conflicting interleaved memory access operations.

9. The memory device of claim 1 , wherein the one or more registers comprise a plurality of registers for storing a plurality of the predefined access profiles.

10. A memory device comprising:

one or more predefined access profiles to determine how access to the memory device is configured for at least one usage of the memory device;

a controller configured to:

receive at least one first command to activate at least one of the one or more predefined access profiles associated with the memory device; and

receive at least one second command to configure access to the memory device in accordance with the at least one of the one or more predefined access profiles such that at least a portion of the memory device is configured according to the at least one of the one or more predefined access profiles for the at least one usage.

11. The memory device of claim 10 , wherein the at least one first command activates two or more access profiles in parallel.

12. The memory device of claim 10 , wherein at least one of the one or more predefined access profiles comprises a default access profile.

13. The memory device of claim 10 , wherein the memory device comprises an embedded MultiMedia Card (eMMC) device.

14. The memory device of claim 10 , wherein the controller is configured to conduct two or more simultaneous memory access operations.

15. The memory device of claim 14 , wherein the controller is configured to assign access priority levels to resolve conflicting simultaneous memory access operations.

16. The memory device of claim 10 , wherein the controller is configured to interleave two or more simultaneous memory access operations.

17. The memory device of claim 16 , wherein the controller is configured to assign access priority levels to resolve conflicting interleaved memory access operations.

18. The memory device of claim 10 , wherein the one or more predefined access profiles comprise a plurality of predefined access profiles.

19. A method comprising:

receiving at least one first command to activate at least one of one or more predefined access profiles associated with a memory device, the one or more predefined access profiles stored in one or more registers, the one or more predefined access profiles determining how access to the memory device is configured for at least one usage of the memory device; and

receiving at least one second command to designate the at least one of the one or more predefined access profiles such that at least a portion of the memory device is configured according to the at least one of the one or more predefined access profiles for the at least one usage.

20. The method of claim 19 , wherein receiving the at least one first command activates two or more access profiles in parallel.

21. The method of claim 19 , wherein at least one of the one or more predefined access profiles comprises a default access profile.

22. The method of claim 19 , wherein the memory device comprises an embedded MultiMedia Card (eMMC) device.

23. The method of claim 19 , further comprising performing two or more memory access operations simultaneously.

24. The method of claim 23 , further comprising assigning access priority levels to resolve conflicting simultaneous memory access operations.

25. The method of claim 19 , further comprising interleaving two or more simultaneous memory access operations.

26. The method of claim 25 , further comprising assigning access priority levels to resolve conflicting interleaved memory access operations.

27. The method of claim 19 , wherein the one or more registers comprise a plurality of registers for storing a plurality of the predefined access profiles.

28. A method comprising:

receiving at least one first command to activate at least one of one or more predefined access profiles associated with a memory device, the one or more predefined access profiles determining how access to the memory device is configured for at least one usage of the memory device; and

receiving at least one second command to configure access to the memory device in accordance with the at least one of the one or more predefined access profiles such that at least a portion of the memory device is configured according to the one or more predefined access profiles for the at least one usage.

29. The method of claim 28 , wherein receiving the at least one first command activates two or more access profiles in parallel.

30. The method of claim 28 , wherein at least one of the one or more predefined access profiles comprises a default access profile.

31. The method of claim 28 , wherein the memory device comprises an embedded MultiMedia Card (eMMC) device.

32. The method of claim 28 , further comprising performing two or more memory access operations simultaneously.

33. The method of claim 32 , further comprising assigning access priority levels to resolve conflicting simultaneous memory access operations.

34. The method of claim 28 , further comprising interleaving two or more simultaneous memory access operations.

35. The method of claim 34 , further comprising assigning access priority levels to resolve conflicting interleaved memory access operations.

36. The method of claim 28 , wherein the one or more predefined access profiles comprise a plurality of predefined access profiles.

37. A host device, comprising:

an interface to couple the host device to a memory device; and

a controller configured with logic instructions to perform acts comprising:

sending at least one first command from the host device to the memory device, the at least one first command to activate at least one of one or more predefined access profiles associated with the memory device, the one or more predefined access profiles stored in one or more registers of the memory device, the one or more predefined access profiles determining how access to the memory device is configured for at least one usage of the memory device; and

sending at least one second command to designate the at least one of the one or more predefined access profiles such that at least a portion of the memory device is configured according to the at least one of the one or more predefined access profiles for the at least one usage.

38. The host device of claim 37 , wherein sending the at least one first command activates two or more access profiles in parallel.

39. The host device of claim 37 , wherein at least one of the one or more predefined access profiles comprises a default access profile.

40. The host device of claim 37 , wherein the memory device comprises an embedded MultiMedia Card (eMMC) device.

41. The host device of claim 37 , wherein at least one of the one or more predefined access profiles configures the memory device to perform two or more memory access operations simultaneously.

42. The host device of claim 41 , wherein at least one of the one or more predefined access profiles configures the memory device to assign access priority levels to resolve conflicting simultaneous memory access operations.

43. The host device of claim 37 , wherein at least one of the one or more predefined access profiles configures the memory device to interleave two or more simultaneous memory access operations.

44. The host device of claim 43 , wherein at least one of the one or more predefined access profiles configures the memory device to assign access priority levels to resolve conflicting interleaved memory access operations.

45. The host device of claim 37 , wherein the one or more registers comprise a plurality of registers for storing a plurality of the predefined access profiles.

46. A host device, comprising:

an interface to couple the host device to a memory device; and

a controller configured with logic instructions to perform acts comprising:

sending at least one first command from the host device to a memory device that is connected to the host device, the at least one first command to activate at least one of one or more predefined access profiles associated with the memory device, the one or more predefined access profiles determining how access to the memory device is configured for at least one usage of the memory device; and

sending at least one second command to configure access to the memory device in accordance with the at least one of the one or more predefined access profiles such that at least a portion of the memory device is configured according to the at least one of the one or more predefined access profiles for the at least one usage.

47. The host device of claim 46 , wherein sending the at least one first command activates two or more access profiles in parallel.

48. The host device of claim 46 , wherein at least one of the one or more predefined access profiles comprises a default access profile.

49. The host device of claim 46 , wherein the memory device comprises an embedded MultiMedia Card (eMMC) device.

50. The host device of claim 46 , wherein at least one of the one or more predefined access profiles configures the memory device to perform two or more memory access operations simultaneously.

51. The host device of claim 50 , wherein at least one of the one or more predefined access profiles configures the memory device to assign access priority levels to resolve conflicting simultaneous memory access operations.

52. The host device of claim 46 , wherein at least one of the one or more predefined access profiles configures the memory device to interleave two or more simultaneous memory access operations.

53. The host device of claim 52 , wherein at least one of the one or more predefined access profiles configures the memory device to assign access priority levels to resolve conflicting interleaved memory access operations.

54. The host device of claim 46 , wherein the one or more predefined access profiles comprise a plurality of predefined access profiles.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2015
From: HYVONEN, JANI; MYLLY, KIMMO; HAKKINEN, JUSSI; GYL, YEVGEN
To: NOKIA CORPORATION
Reel/Frame 035068/0806 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2015
From: NOKIA CORPORATION
To: NOKIA INC.
Reel/Frame 035068/0854 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2015
From: NOKIA INC.
To: MEMORY TECHNOLOGIES LLC
Reel/Frame 035068/0929 →
Continuity (3)
Continuation 12039672 · Feb 28, 2008
Continuation 13645588 · Oct 5, 2012
Related Publication 20130332691A1 · Dec 12, 2013