MEMORY CELL WITH INDEPENDENTLY-SIZED ELEMENTS

1 . A memory cell, comprising:

a switch element; and

a memory element formed in series with the switch element,

wherein a smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.

2 . The memory cell of claim 1 , wherein the smallest lateral dimension of the switch element is greater than the smallest lateral dimension of the memory element.

3 . The memory cell of claim 2 , wherein the smallest lateral dimension of the switch element is a critical dimension of the switch element.

4 . The memory cell of claim 2 , further comprising an electrode, wherein the switch element, the memory element, and the electrode are arranged in a stack, and wherein the smallest lateral dimension of the memory element is less than a smallest lateral dimension of the electrode.

5 . The memory cell of claim 4 , wherein the electrode is located between the switch element and the memory element.

6 . The memory cell of claim 5 , wherein a cross-sectional area of the switch element in a plane perpendicular to a stack length is less than a cross-sectional area of the electrode in a plane perpendicular to a stack length.

7 . The memory cell of claim 1 , wherein the smallest lateral dimension of the switch element is less than the smallest lateral dimension of the memory element.

8 . The memory cell of claim 7 , wherein the smallest lateral dimension of the memory element is a critical dimension of the memory element.

9 . The memory cell of claim 7 , further comprising an electrode, wherein the switch element, the memory element, and the electrode are arranged in a stack, and wherein the smallest lateral dimension of the switch element is less than a smallest lateral dimension of the electrode.

10 . The memory cell of claim 9 , wherein the electrode is located between the switch element and the memory element.

11 . The memory cell of claim 10 , wherein a cross-sectional area of the switch element in a plane perpendicular to a stack length is less than a cross-sectional area of the electrode in a plane perpendicular to a stack length.

12 . The memory cell of claim 1 , wherein the switch element and the memory element are arranged in a stack, and wherein a cross-sectional area of the switch element in a plane perpendicular to a stack length is less than a cross-sectional area of the memory element in a plane perpendicular to a stack length.

13 . The memory cell of claim 1 , wherein the switch element and the memory element are arranged in a stack, and wherein a cross-sectional area of the switch element in a plane perpendicular to a stack length is greater than a cross-sectional area of the memory element in a plane perpendicular to a stack length.

14 . A memory cell, comprising:

a switch element; and

a memory element corresponding to the switch element,

wherein a modified lateral dimension of a first one of the switch element or memory element is different than a smallest lateral dimension of a second one of the switch element or memory element.

15 . The memory cell of claim 14 , wherein the modified lateral dimension of the memory element is smaller than a critical dimension of the switch element.

16 . The memory cell of claim 14 , wherein the modified lateral dimension of the memory element is smaller than a modified lateral dimension of the switch element.

17 . A method for forming a memory cell, comprising:

forming a switch element;

forming a memory element in series with the switch element; and

changing at least one of a smallest lateral dimension of the switch element and a smallest lateral dimension of the memory element such that the smallest lateral dimension of the switch element is different than the smallest lateral dimension of the memory element.

18 . The method of claim 17 , wherein changing at least one of the smallest lateral dimension of the switch element and the smallest lateral dimension of the memory element includes reducing the smallest lateral dimension of the memory element to be less than the smallest lateral dimension of switch element.

19 . The method of claim 17 , wherein changing at least one of the smallest lateral dimension of the switch element and the smallest lateral dimension of the memory element includes reducing the smallest lateral dimension of the switch element and reducing the smallest lateral dimension of the memory element to be less than the smallest lateral dimension of the switching element.

20 . The method of claim 17 , wherein changing at least one of the smallest lateral dimension of the switch element and the smallest lateral dimension of the memory element includes reducing the smallest lateral dimension of the switch element to be less than the smallest lateral dimension of memory element.

21 . The method of claim 17 , wherein changing at least one of the smallest lateral dimension of the switch element and the smallest lateral dimension of the memory element includes reducing the smallest lateral dimension of the memory element and reducing the smallest lateral dimension of the switch element to be less than the smallest lateral dimension of the memory element.

22 . The method of claim 17 , wherein changing at least one of the smallest lateral dimension of the switch element and the smallest lateral dimension of the memory element includes reducing a cross-sectional area of the switch element in a plane perpendicular to a direction between the switch element and the memory element such that the cross-sectional area of the switch element is less than the cross-sectional area of the memory element.

23 . The method of claim 17 , wherein changing at least one of the smallest lateral dimension of the switch element and the smallest lateral dimension of the memory element includes reducing a cross-sectional area of the memory element in a plane perpendicular to a direction between the switch element and the memory element such that the cross-sectional area of the memory element is less than the cross-sectional area of the switch element.

24 . The method of claim 17 , wherein changing at least one of the smallest lateral dimension of the switch element and the smallest lateral dimension of the memory element includes reducing a cross-sectional area of the switch element and the memory element in a plane perpendicular to a direction between the switch element and the memory element.

25 . A method for forming a memory cell, comprising:

forming a stack of materials, the stack of materials including an electrode located between a memory element and a switch element;

etching, via a directional process, a first one of the switch element or the memory element before etching the electrode;

etching, via a selective/isotropic process before etching the electrode, the first one of the switch element or the memory element;

etching the electrode; and

etching a second one of the switch element or the memory element.

26 . The method of claim 25 , wherein etching, via the directional process, the first one of the switch element or the memory element includes etching the memory element, and wherein etching the second one of the switch element or the memory element includes etching the switch element.

27 . The method of claim 25 , wherein etching, via the selective/isotropic process, the first one of the switch element or the memory element includes etching the first one of the switch element or the memory element to a smallest lateral dimension that is less than a smallest lateral dimension to which the second one of the switch element or the memory element is to be etched.

28 . The method of claim 25 , wherein etching, via the directional process, the first one of the switch element or the memory element includes etching the switch element, and wherein etching the second one of the switch element or the memory element includes etching the memory element.

29 . The method of claim 25 , further comprising etching, via the selective/isotropic process, the second one of the switch element or the memory element.

30 . The method of claim 29 , wherein etching, via the selective/isotropic process, the second one of the switch element or the memory element includes etching the second one of the switch element or the memory element to a smallest lateral dimension that is less than a smallest lateral dimension of the first one of the switch element or the memory element.

31 . A method for forming a memory cell, comprising:

forming a stack of materials, the stack of materials including a first electrode, a switch element, a second electrode, a memory element, and a third electrode;

etching the third electrode;

etching, via a first directional process, the memory element after etching the third electrode;

etching, via a first selective/isotropic process, the memory element;

etching the second electrode after etching the memory element via the first directional etch;

etching, via a second directional process, the switch element; and

etching the first electrode,

wherein the memory element is etched to a different smallest lateral dimension than a smallest lateral dimension to which the switch element is etched.

32 . The method of claim 31 , wherein the memory element is etched via the first selective/isotropic process to a smaller lateral dimension than the smallest lateral dimension to which the switch element is etched via the second directional process.

33 . The method of claim 31 , further comprising etching, via a second selective/isotropic process, the switch element, wherein the second selective/isotropic process is selective to a different material than the first selective/isotropic process.

34 . The method of claim 33 , wherein the switch element is etched via the second selective/isotropic process to a greater lateral dimension than the smallest lateral dimension to which the memory element is etched via the first selective/isotropic process.

35 . The method of claim 33 , wherein the switch element is etched via the second selective/isotropic process to a smaller lateral dimension than the smallest lateral dimension to which the memory element is etched via the first selective/isotropic process.