Electric charge flow element
An electric charge flow element including, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.
1. An electric charge flow element comprising, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.
2. The element of claim 1 , wherein one of the electrodes is made of heavily-doped polysilicon.
3. The element of claim 1 , wherein both electrodes are made of undoped polysilicon.
4. The element of claim 1 , wherein said dielectric layer comprises an oxide-nitride-oxide stack, said at least one portion being made of silicon oxide.
5. The element of claim 1 , having a capacitance between the two electrodes ranging between 1*10 −15 and 10*10 −15 farads.
6. A use of the element of claim 1 , for a time measurement.
7. An electric charge retention circuit, comprising:
a capacitive charge storage element; and
a charge flow element electrically coupled to the capacitive charge storage element and including, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.
8. The circuit of claim 7 , wherein the capacitive storage element has a capacitance ranging between 10 −12 and 100*10 −12 farads.
9. The circuit of claim 7 , further comprising a capacitive initialization element connected to a floating node common to the storage element and to the flow element.
10. The circuit of claim 9 , wherein the capacitive initialization element has a capacitance ranging between 10*10 −15 and 100*10 −15 farads.
11. The circuit of claim 7 , wherein both electrodes are made of undoped polysilicon.
12. An integrated circuit chip formed inside and on top of a semiconductor substrate, comprising:
non-volatile memory cells,
logic blocks including MOS transistors, and
an electric charge retention circuit including:
a capacitive charge storage element; and
a charge flow element electrically coupled to the capacitive charge storage element and including on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.
13. The integrated circuit chip of claim 12 , wherein the capacitive storage element has a capacitance ranging between 10 −12 and 100*10 −12 farads.
14. The integrated circuit chip of claim 12 , wherein the electric charge retention circuit includes a capacitive initialization element connected to a floating node common to the storage element and to the flow element.
15. The integrated circuit chip of claim 12 , wherein both electrodes are made of undoped polysilicon.