Iterative decoding of blocks with cyclic redundancy checks
View Patent ↗The iterative decoding of blocks may be continued or terminated based on CRC checks. In an example embodiment, one iteration of an iterative decoding process is performed on a block whose information bits are covered by a CRC. The iterative decoding process is stopped if the CRC checks for a predetermined number of consecutive iterations. In another example embodiment, a decoding iteration is performed on a particular sub-block of multiple sub-blocks of a transport block, which includes a single CRC over an entirety of the transport block. The CRC is checked using decoded bits obtained from the decoding iteration on the particular sub-block and decoded bits obtained from previous decoding iterations on other sub-blocks of the multiple sub-blocks. The decoding iteration is then performed on a different sub-block if the CRC does not check. Also, the decoding iterations for the sub-blocks may be terminated if the CRC checks.
1. A method for decoding a transport block including multiple sub-blocks, each of which can be decoded iteratively, wherein the transport block also includes a single cyclic redundancy check, CRC, over an entirety of the transport block; the method comprising acts of:
performing a decoding iteration on a particular sub-block of the multiple sub-blocks;
checking the CRC for the entirety of the transport block using decoded bits obtained from the decoding iteration on the particular sub-block and decoded bits obtained from a most recent decoding iteration on other sub-blocks of the multiple sub-blocks; and
performing a decoding iteration on a different sub-block if the CRC does not check.
2. A method for decoding a transport block including multiple sub-blocks, each of which can be decoded iteratively, wherein the transport block also includes a single cyclic redundancy check, CRC, over an entirety of the transport block; the method comprising acts of:
performing a decoding iteration on a particular sub-block of the multiple sub-blocks;
checking the CRC for the entirety of the transport block using decoded bits obtained from the decoding iteration on the particular sub-block and decoded bits obtained using a most recent decoding iteration on other sub-blocks of the multiple sub-blocks; and
terminating the decoding iterations for all of the sub-blocks of the multiple sub-blocks if the CRC checks consecutively for a predetermined number of consecutive decoding iterations.
3. The method as recited in claim 2 wherein the consecutive decoding iterations may be on different sub-blocks of the multiple sub-blocks.
4. The method as recited in claim 2 , wherein the acts of checking and terminating are skipped until after a predetermined minimum number of the decoding iterations have been performed on the particular sub-block.
5. The method as recited in claim 2 , wherein the act of terminating is skipped until after the acts of performing and checking have been implemented a predetermined minimum number of times.
6. A method for iterative decoding of a transport block having a cyclic redundancy check, CRC, the method comprising acts of:
receiving a transport block having multiple sub-blocks, the transport block including a CRC associated with the multiple sub-blocks;
performing a decoding iteration on a number of sub-blocks of the multiple sub-blocks;
ascertaining if the CRC checks with regard to the multiple sub-blocks; and
performing the decoding iteration on at least one different sub-block of the multiple sub-blocks if the CRC is not ascertained to check.
7. The method as recited in claim 6 , further comprising an act of:
performing the decoding iteration on each of the sub-blocks of the multiple sub-blocks at least once prior to performing the act of ascertaining.
8. The method as recited in claim 6 , wherein the number of sub-blocks for the act of performing a decoding iteration on a number of sub-blocks equals one.
9. The method as recited in claim 6 , further comprising an act of:
if the CRC is ascertained to check, declaring the transport block valid.
10. The method as recited in claim 6 , further comprising an act of:
if the CRC is ascertained to check, repeatedly performing the decoding iterations on one or more sub-blocks until a CRC checking history is determined to meet a predetermined criterion.
11. The method as recited in claim 10 , wherein:
the CRC checking history is determined to meet the predetermined criterion if the CRC checks a predetermined total number of times; or
the CRC checking history is determined to meet the predetermined criterion if the CRC checks a predetermined consecutive number of times.
12. The method as recited in claim 10 , further comprising an act of:
declaring the transport block invalid if the CRC checking history is not determined to meet the predetermined criterion.
13. The method as recited in claim 6 , further comprising an act of:
declaring the transport block invalid if a predetermined number of decoding iterations are performed on each sub-block of the multiple sub-blocks without the CRC checking.
14. A device for iterative decoding of a transport block having a cyclic redundancy check, CRC, the device comprising:
a receiver to receive a transport block having multiple sub-blocks, the transport block including a CRC associated with the multiple sub-blocks;
a decoder to decode a subset of the multiple sub-blocks; and
at least one processor programmed to ascertain if the CRC checks with regard to the multiple sub-blocks after the subset is decoded by the decoder, the processor programmed to cause the decoder to continue to iteratively decode other subsets of the multiple sub-blocks if the CRC is not ascertained to check after each of the subsets.
15. The device as recited in claim 14 , wherein the decoder comprises a turbo decoder that performs two decoding operations per decoding cycle.
16. The device as recited in claim 15 , wherein each iteration of the turbo decoder comprises one decoding operation or two decoding operations.
17. The device as recited in claim 14 , wherein the processor is further programmed (i) to prioritize respective ones of the multiple sub-blocks based on respective sub-block reliability values and (ii) to cause the decoder to decode the subsets of the multiple sub-blocks responsive to the sub-block reliability value prioritization.
18. The device as recited in claim 14 , wherein the processor is further programmed to ascertain if the CRC checks with regard to the multiple sub-blocks by checking decoded bits that are concatenated from a current decoding iteration on the subset of the multiple sub-blocks and from a most recent decoding iteration for one or more other sub-blocks of the multiple sub-blocks.
19. The device as recited in claim 14 , wherein the processor is further programmed to repeatedly decode subsets of the multiple sub-blocks until a CRC checking history is determined to meet a predetermined criterion.
20. The device as recited in claim 19 , wherein:
the CRC checking history is determined to meet the predetermined criterion if the CRC checks a predetermined total number of times; or
the CRC checking history is determined to meet the predetermined criterion if the CRC checks a predetermined consecutive number of times.
21. A non-transitory memory storing processor-executable instructions for iterative decoding of a transport block having a cyclic redundancy check, CRC, wherein the processor-executable instructions, when executed, direct a device to perform acts comprising:
receiving a transport block having multiple sub-blocks, the transport block including a CRC associated with the multiple sub-blocks, the multiple sub-blocks numbering “n”;
performing a decoding iteration on a number of sub-blocks of the multiple sub-blocks, the number being greater than zero and less than “n”;
ascertaining if the CRC checks with regard to the multiple sub-blocks; and
performing the decoding iteration on at least one different sub-block of the multiple sub-blocks if the CRC is not ascertained to check.