Gallium nitride (GaN) device with leakage current-based over-voltage protection
View Patent ↗A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region.
1. A gallium nitride (GaN) device with leakage current-based over-voltage protection comprising:
a semiconductor substrate;
a drain disposed on the semiconductor substrate;
a source disposed on the semiconductor substrate;
a first channel region within the semiconductor substrate and between the drain and the source;
a second channel region within the semiconductor substrate and between the drain and the source wherein the second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region;
a gate having gate segments disposed on the substrate adjacent to the second channel region; and
an insulator extending between the gate segments and the semiconductor substrate, wherein the DIBL of the second channel region is controlled by a thickness of the insulator.
2. The GaN device of claim 1 wherein the DIBL of the first channel region ranges from less than around about 0.001 V/V.
3. The GaN device of claim 2 wherein the DIBL of the second channel region ranges from around about 0.003 V/V to around about 0.03 V/V.
4. The GaN device of claim 1 wherein the DIBL of the second channel region is controlled by an interval distance between adjacent gate segments.
5. The GaN device of claim 4 wherein the gate is directly disposed on the semiconductor substrate.
6. The GaN device of claim 5 further including a gate strap that electrically couples the adjacent gate segments.
7. The GaN device of claim 6 wherein the DIBL of the second channel region is further controlled by a distance of the gate strap from the semiconductor substrate.
8. The GaN device of claim 1 further including a gate strap that electrically couples the adjacent gate segments.
9. The GaN device of claim 8 wherein the DIBL of the second channel region is further controlled by a distance of the gate strap from the semiconductor substrate.
10. The GaN device of claim 1 wherein the first channel region and the second channel region are one and the same.
11. The GaN device of claim 1 wherein the second channel region accounts for a range of around about 0.1% to around about 10% of a total channel periphery made up of the first channel region and the second channel region.
12. The GaN device of claim 1 wherein the second channel region accounts for a range of around about 10% to around about 50% of a total channel periphery made up of the first channel region and the second channel region.
13. The GaN device of claim 1 wherein the second channel region accounts for a range of around about 50% to around about 100% of a total channel periphery made up of the first channel region and the second channel region.
14. The GaN device of claim 1 wherein a drain voltage level for when the second channel region begins to conduct electricity ranges from around about 600 V to around about 1400 V.